Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

VLSI System Design

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Electrical Engineering (EE) : Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

The document Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev is a part of the Electrical Engineering (EE) Course VLSI System Design.
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Objectives

In this lecture you will learn the following

  • Introduction
  • Different Configurations with NMOS Inverter
  • Worries about Pseudo NMOS Inverter
  • Calculation of Capacitive Load

17.1 Introduction

The inverter that uses a p-device pull-up or load that has its gate permanently ground. An n-device pull-down or driver is driven with the input signal. This roughly equivalent to use of a depletion load is Nmos technology and is thus called ‘Pseudo-NMOS’. The circuit is used in a variety of CMOS logic circuits. In this, PMOS for most of the time will be linear region. So resistance is low and hence RC time constant is low. When the driver is turned on a constant DC current flows in the circuit.

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Fig 17.1: CMOS Inverter Circuit

 

17.2 Different Configurations with NMOS Inverter

Cascade pseudo NMOS invertor:
Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Saturated n-mosNMOS invertor:

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

More saturated NMOS Load invertor:

 

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev


17.3 CMOS Summary

Logic consumes no static power in CMOS design style. However, signals have to be routed to the n pull down network as well as to the p pull up network. So the load presented to every driver is high. This is exacerbated by the fact that n and p channel transistors cannot be placed close together as these are in different wells which have to be kept well separated in order to avoid latchup.

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev  Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

 

17.4 Pseudo nMOS Design Style

The CMOS pull up network is replaced by a single pMOS transistor with its gate grounded. Since the pMOS is not driven by signals, it is always ‘on'. The effective gate voltage seen by the pMOS transistor is Vdd. Thus the overvoltage on the p channel gate is always Vdd -VTp. When the nMOS is turned ‘on', a direct path between supply and ground exists and static power will be drawn. However, the dynamic power is reduced due to lower capacitive loading.


17.5 Static Characteristics

As we sweep the input voltage from ground to , we
encounter the following regimes of operation:

  • nMOS ‘off’
  • nMOS saturated, pMOS linear
  • nMOS linear, pMOS linear
  • nMOS linear, pMOS saturated


17.6 Low input

  • When the input voltage is less than VTn.
  • The output is ‘high’ and no current is drawn from the supply
  • As we raise the input just above VTn, the output starts falling.
  • In this region the nMOS is saturated, while the pMOS is linear.


17.7 nMOS saturated, pMOS linear

The input voltage is assumed to be sufficiently low so that the output voltage exceeds the saturation voltage V- VTn. Normally, this voltage will be higher than VTp, so the p channel transistor is in linear mode of operation. Equating currents through the n and p channel transistors, we get 

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

defining  Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev and  Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev We get

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

The solutions are:

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

substituting the values of Vand Vand choosing the sign which puts Vin the correct range, we get

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

  • As the input voltage is increased, the output voltage will decrease.
  • The output voltage will fall below V- VTnwhen

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

The nMOS is now in its linear mode of operation. The derived equation does not apply beyond this input voltage.

 

 

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

 

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

Pseudo NMOS Inverter (Part - 1) Electrical Engineering (EE) Notes | EduRev

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