Question & Answers on Computer Architecture Computer Science Engineering (CSE) Notes | EduRev

Computer Science Engineering (CSE) : Question & Answers on Computer Architecture Computer Science Engineering (CSE) Notes | EduRev

 Page 1


AC07/AT07                                                                       Computer Architecture 
 
 
 1 
TYPICAL QUESTIONS & ANSWERS 
PART - I 
OBJECTIVE TYPE QUESTIONS 
Each Question carries 2 marks. 
Choose correct or the best alternative in the following: 
Q.1 In a virtual memory system, the addresses used by the programmer belongs to 
 (A) memory space.               (B) physical addresses.  
 (C) address space.                (D) main memory address. 
  
 Ans: C 
 An address used by programmers in a system supporting virtual memory concept is 
 called virtual address and the set of such addresses are called address space. 
 
Q.2  The method for updating the main memory as soon as a word is removed from the    
  Cache is called 
 (A) Write-through                  (B) write-back  
 (C) protected write                 (D) cache-write 
  
 Ans: B 
 In this method only cache location is updated during write operation. 
 
Q.3 A control character is sent at the beginning as well as at the end of each block in the 
 synchronous-transmission in order to 
 (A) Synchronize the clock of transmitter and receiver. 
 (B) Supply information needed to separate the incoming bits into individual  
        character. 
 (C) Detect the error in transmission and received system. 
 (D) Both (A) and (C). 
  
 Ans B 
 As the data are sent continuously as a block of data at the rate dictated by the clock 
 frequency, so the receiver should be supplied with the same function about the same 
 bit length in order to interrupt the information.  
 
Q.4  In a non-vectored interrupt, the address of interrupt service routine is 
 (A) Obtained from interrupt address table. 
 (B) Supplied by the interrupting I/O device. 
 (C) Obtained through Vector address generator device. 
 (D) Assigned to a fixed memory location. 
  
 Ans: D 
 The source device that interrupted the processor supply the vector address which 
 helps processor to find out the actual memory location where ISR is stored for the 
 device. 
Page 2


AC07/AT07                                                                       Computer Architecture 
 
 
 1 
TYPICAL QUESTIONS & ANSWERS 
PART - I 
OBJECTIVE TYPE QUESTIONS 
Each Question carries 2 marks. 
Choose correct or the best alternative in the following: 
Q.1 In a virtual memory system, the addresses used by the programmer belongs to 
 (A) memory space.               (B) physical addresses.  
 (C) address space.                (D) main memory address. 
  
 Ans: C 
 An address used by programmers in a system supporting virtual memory concept is 
 called virtual address and the set of such addresses are called address space. 
 
Q.2  The method for updating the main memory as soon as a word is removed from the    
  Cache is called 
 (A) Write-through                  (B) write-back  
 (C) protected write                 (D) cache-write 
  
 Ans: B 
 In this method only cache location is updated during write operation. 
 
Q.3 A control character is sent at the beginning as well as at the end of each block in the 
 synchronous-transmission in order to 
 (A) Synchronize the clock of transmitter and receiver. 
 (B) Supply information needed to separate the incoming bits into individual  
        character. 
 (C) Detect the error in transmission and received system. 
 (D) Both (A) and (C). 
  
 Ans B 
 As the data are sent continuously as a block of data at the rate dictated by the clock 
 frequency, so the receiver should be supplied with the same function about the same 
 bit length in order to interrupt the information.  
 
Q.4  In a non-vectored interrupt, the address of interrupt service routine is 
 (A) Obtained from interrupt address table. 
 (B) Supplied by the interrupting I/O device. 
 (C) Obtained through Vector address generator device. 
 (D) Assigned to a fixed memory location. 
  
 Ans: D 
 The source device that interrupted the processor supply the vector address which 
 helps processor to find out the actual memory location where ISR is stored for the 
 device. 
AC07/AT07                                                                       Computer Architecture 
 
 
 2 
Q.5 Divide overflow is generated when 
 (A) Sign of the dividend is different from that of divisor. 
 (B) Sign of the dividend is same as that of divisor. 
 (C) The first part of the dividend is smaller than the divisor. 
 (D) The first part of the dividend is greater than the divisor. 
  
 Ans: B 
 If the first part of the dividend is greater than the deviser, then the result should be 
 of greater length, then that can be hold in a register of the system. The registers are 
 of fixed length in  
 any processor. 
 
Q.6 Which method is used for resolving data dependency conflict by the compiler 
 itself? 
 (A) Delayed load.                 (B) operand forwarding.  
 (C) Pre fetch target instruction.          (D) loop buffer. 
  
 Ans: A 
 In case of delayed load technique the complier detects the data conflict and reorder 
 the instruction as necessary to delay the loading of the conflicting data by inserting 
 no operation instructions. 
 
Q.7  Stack overflow causes  
 (A) Hardware interrupt. 
 (B) External interrupt.  
         (C) Internal interrupt.  
 (D) Software interrupt. 
  
 Ans: C 
 Stack overflow occurs while execution of a program due to logical faults. So it is a 
 program dependent, hence interrupt activated. 
 
Q.8 Arithmetic shift left operation 
 (A) Produces the same result as obtained with logical shift left operation. 
 (B) Causes the sign bit to remain always unchanged. 
 (C) Needs additional hardware to preserve the sign bit. 
 (D) Is not applicable for signed 2's complement representation. 
  
 Ans:  A 
 If the register hold minus five in two’s compliment form than in arithmetic shift left 
 the contents of the register shall be  
                
 It is found that the register contents multiplied by two after logical shift left 
 operation. Hence arithmetic shift left operation is same as logical shift operation. 
 
Page 3


AC07/AT07                                                                       Computer Architecture 
 
 
 1 
TYPICAL QUESTIONS & ANSWERS 
PART - I 
OBJECTIVE TYPE QUESTIONS 
Each Question carries 2 marks. 
Choose correct or the best alternative in the following: 
Q.1 In a virtual memory system, the addresses used by the programmer belongs to 
 (A) memory space.               (B) physical addresses.  
 (C) address space.                (D) main memory address. 
  
 Ans: C 
 An address used by programmers in a system supporting virtual memory concept is 
 called virtual address and the set of such addresses are called address space. 
 
Q.2  The method for updating the main memory as soon as a word is removed from the    
  Cache is called 
 (A) Write-through                  (B) write-back  
 (C) protected write                 (D) cache-write 
  
 Ans: B 
 In this method only cache location is updated during write operation. 
 
Q.3 A control character is sent at the beginning as well as at the end of each block in the 
 synchronous-transmission in order to 
 (A) Synchronize the clock of transmitter and receiver. 
 (B) Supply information needed to separate the incoming bits into individual  
        character. 
 (C) Detect the error in transmission and received system. 
 (D) Both (A) and (C). 
  
 Ans B 
 As the data are sent continuously as a block of data at the rate dictated by the clock 
 frequency, so the receiver should be supplied with the same function about the same 
 bit length in order to interrupt the information.  
 
Q.4  In a non-vectored interrupt, the address of interrupt service routine is 
 (A) Obtained from interrupt address table. 
 (B) Supplied by the interrupting I/O device. 
 (C) Obtained through Vector address generator device. 
 (D) Assigned to a fixed memory location. 
  
 Ans: D 
 The source device that interrupted the processor supply the vector address which 
 helps processor to find out the actual memory location where ISR is stored for the 
 device. 
AC07/AT07                                                                       Computer Architecture 
 
 
 2 
Q.5 Divide overflow is generated when 
 (A) Sign of the dividend is different from that of divisor. 
 (B) Sign of the dividend is same as that of divisor. 
 (C) The first part of the dividend is smaller than the divisor. 
 (D) The first part of the dividend is greater than the divisor. 
  
 Ans: B 
 If the first part of the dividend is greater than the deviser, then the result should be 
 of greater length, then that can be hold in a register of the system. The registers are 
 of fixed length in  
 any processor. 
 
Q.6 Which method is used for resolving data dependency conflict by the compiler 
 itself? 
 (A) Delayed load.                 (B) operand forwarding.  
 (C) Pre fetch target instruction.          (D) loop buffer. 
  
 Ans: A 
 In case of delayed load technique the complier detects the data conflict and reorder 
 the instruction as necessary to delay the loading of the conflicting data by inserting 
 no operation instructions. 
 
Q.7  Stack overflow causes  
 (A) Hardware interrupt. 
 (B) External interrupt.  
         (C) Internal interrupt.  
 (D) Software interrupt. 
  
 Ans: C 
 Stack overflow occurs while execution of a program due to logical faults. So it is a 
 program dependent, hence interrupt activated. 
 
Q.8 Arithmetic shift left operation 
 (A) Produces the same result as obtained with logical shift left operation. 
 (B) Causes the sign bit to remain always unchanged. 
 (C) Needs additional hardware to preserve the sign bit. 
 (D) Is not applicable for signed 2's complement representation. 
  
 Ans:  A 
 If the register hold minus five in two’s compliment form than in arithmetic shift left 
 the contents of the register shall be  
                
 It is found that the register contents multiplied by two after logical shift left 
 operation. Hence arithmetic shift left operation is same as logical shift operation. 
 
AC07/AT07                                                                       Computer Architecture 
 
 
 3 
Q.9 Zero address instruction format is used for 
 (A) RISC architecture.      
       (B) CISC architecture. 
 (C) Von-Neuman architecture.  
 (D) Stack-organized architecture. 
  
 Ans: D 
 In stack organized architecture push and pop instruction is needs a address field to 
 specify the location of data for pushing into the stack and destination location 
 during pop operation but for logic and arithmetic operation the instruction does not 
 need any address field as it operates on the top two data available in the stack. 
 
Q.10  Address symbol table is generated by the 
 (A) memory management software. 
 (B) assembler. 
 (C) match logic of associative memory.  
 (D) generated by operating system 
  
 Ans: B 
 During the first pass of assembler address symbol table is generated which contains 
 the label used by the programmer and its actual address with reference to the stored 
 program. 
 
Q.11  The ASCII code for letter A is 
  (A)  1100011   (B)  1000001 
  (C)  1111111   (D)  0010011 
   
  Ans. (B)  
 
Q.12 The simplified expression of (A+B) +  C is 
 (A) (A + B)C  (B) A(B + C) 
 (C) (C+A + B)  (D) None of these 
  
 Ans.  (A) 
   
Q.13 The negative numbers in the binary system can be represented by 
 (A)  Sign magnitude (B) I's complement 
 (C)  2's complement (D) All of the above 
  
 Ans. (C)  
 
Q.14 ABCD - seven segment decoder / driver in connected to an LED display.  
 Which segments are illuminated for the input code DCBA = 0001. 
 (A)b, c    (B) c, b 
 (C)a, b, c   (D) a, b, c, d 
  
 Ans. (A)  
 
Q.15 How many flip-flops are required to produce a divide-by-32 device? 
 (A)4    (B) 6 
Page 4


AC07/AT07                                                                       Computer Architecture 
 
 
 1 
TYPICAL QUESTIONS & ANSWERS 
PART - I 
OBJECTIVE TYPE QUESTIONS 
Each Question carries 2 marks. 
Choose correct or the best alternative in the following: 
Q.1 In a virtual memory system, the addresses used by the programmer belongs to 
 (A) memory space.               (B) physical addresses.  
 (C) address space.                (D) main memory address. 
  
 Ans: C 
 An address used by programmers in a system supporting virtual memory concept is 
 called virtual address and the set of such addresses are called address space. 
 
Q.2  The method for updating the main memory as soon as a word is removed from the    
  Cache is called 
 (A) Write-through                  (B) write-back  
 (C) protected write                 (D) cache-write 
  
 Ans: B 
 In this method only cache location is updated during write operation. 
 
Q.3 A control character is sent at the beginning as well as at the end of each block in the 
 synchronous-transmission in order to 
 (A) Synchronize the clock of transmitter and receiver. 
 (B) Supply information needed to separate the incoming bits into individual  
        character. 
 (C) Detect the error in transmission and received system. 
 (D) Both (A) and (C). 
  
 Ans B 
 As the data are sent continuously as a block of data at the rate dictated by the clock 
 frequency, so the receiver should be supplied with the same function about the same 
 bit length in order to interrupt the information.  
 
Q.4  In a non-vectored interrupt, the address of interrupt service routine is 
 (A) Obtained from interrupt address table. 
 (B) Supplied by the interrupting I/O device. 
 (C) Obtained through Vector address generator device. 
 (D) Assigned to a fixed memory location. 
  
 Ans: D 
 The source device that interrupted the processor supply the vector address which 
 helps processor to find out the actual memory location where ISR is stored for the 
 device. 
AC07/AT07                                                                       Computer Architecture 
 
 
 2 
Q.5 Divide overflow is generated when 
 (A) Sign of the dividend is different from that of divisor. 
 (B) Sign of the dividend is same as that of divisor. 
 (C) The first part of the dividend is smaller than the divisor. 
 (D) The first part of the dividend is greater than the divisor. 
  
 Ans: B 
 If the first part of the dividend is greater than the deviser, then the result should be 
 of greater length, then that can be hold in a register of the system. The registers are 
 of fixed length in  
 any processor. 
 
Q.6 Which method is used for resolving data dependency conflict by the compiler 
 itself? 
 (A) Delayed load.                 (B) operand forwarding.  
 (C) Pre fetch target instruction.          (D) loop buffer. 
  
 Ans: A 
 In case of delayed load technique the complier detects the data conflict and reorder 
 the instruction as necessary to delay the loading of the conflicting data by inserting 
 no operation instructions. 
 
Q.7  Stack overflow causes  
 (A) Hardware interrupt. 
 (B) External interrupt.  
         (C) Internal interrupt.  
 (D) Software interrupt. 
  
 Ans: C 
 Stack overflow occurs while execution of a program due to logical faults. So it is a 
 program dependent, hence interrupt activated. 
 
Q.8 Arithmetic shift left operation 
 (A) Produces the same result as obtained with logical shift left operation. 
 (B) Causes the sign bit to remain always unchanged. 
 (C) Needs additional hardware to preserve the sign bit. 
 (D) Is not applicable for signed 2's complement representation. 
  
 Ans:  A 
 If the register hold minus five in two’s compliment form than in arithmetic shift left 
 the contents of the register shall be  
                
 It is found that the register contents multiplied by two after logical shift left 
 operation. Hence arithmetic shift left operation is same as logical shift operation. 
 
AC07/AT07                                                                       Computer Architecture 
 
 
 3 
Q.9 Zero address instruction format is used for 
 (A) RISC architecture.      
       (B) CISC architecture. 
 (C) Von-Neuman architecture.  
 (D) Stack-organized architecture. 
  
 Ans: D 
 In stack organized architecture push and pop instruction is needs a address field to 
 specify the location of data for pushing into the stack and destination location 
 during pop operation but for logic and arithmetic operation the instruction does not 
 need any address field as it operates on the top two data available in the stack. 
 
Q.10  Address symbol table is generated by the 
 (A) memory management software. 
 (B) assembler. 
 (C) match logic of associative memory.  
 (D) generated by operating system 
  
 Ans: B 
 During the first pass of assembler address symbol table is generated which contains 
 the label used by the programmer and its actual address with reference to the stored 
 program. 
 
Q.11  The ASCII code for letter A is 
  (A)  1100011   (B)  1000001 
  (C)  1111111   (D)  0010011 
   
  Ans. (B)  
 
Q.12 The simplified expression of (A+B) +  C is 
 (A) (A + B)C  (B) A(B + C) 
 (C) (C+A + B)  (D) None of these 
  
 Ans.  (A) 
   
Q.13 The negative numbers in the binary system can be represented by 
 (A)  Sign magnitude (B) I's complement 
 (C)  2's complement (D) All of the above 
  
 Ans. (C)  
 
Q.14 ABCD - seven segment decoder / driver in connected to an LED display.  
 Which segments are illuminated for the input code DCBA = 0001. 
 (A)b, c    (B) c, b 
 (C)a, b, c   (D) a, b, c, d 
  
 Ans. (A)  
 
Q.15 How many flip-flops are required to produce a divide-by-32 device? 
 (A)4    (B) 6 
AC07/AT07                                                                       Computer Architecture 
 
 
 4 
 (C)5    (D) 7 
  
 Ans. (C)  
 
Q.16 The content of a 4-bit register is initially 1101.  The register is shifted 2 times  to 
 the right with the serial input being 1011101.   
 What is the content of the register after each shift?  
 (A)1110, 0111  (B) 0001, 1000 
 (C)1101, 1011  (D) 1001, 1001 
  
 Ans. (A)  
 
Q.17 How many different addresses are required by the memory that contain 16K 
 words? 
 (A)16,380   (B) 16,382 
 (C)16,384   (D) 16,386 
  
 Ans. (C)  
   
Q.18 What is the bit storage capacity of a ROM with a 512' 4-organization? 
 (A) 2049   (B) 2048 
 (C) 2047   (D) 2046 
  
 Ans. (B)  
 
Q.19 DMA interface unit eliminates the need to use CPU registers to transfer data 
 from 
 (A) MAR to MBR (B) MBR to MAR 
 (C) I/O units to memory (D) Memory to I/O units 
  
 Ans. (D)  
 
Q.20 How many 128 x 8 RAM chips are needed to provide a memory capacity of 
 2048 bytes? 
 (A) 8    (B) 16 
 (C) 24    (D) 32 
  
 Ans.  (B)  
 
Q.21 Which of the following is a self complementing code? 
 (A) 8421 code  (B) 5211 
 (C) Gray code  (D) Binary code 
  
 Ans. (A)   
  
Q.22 Which gate can be used as anti-coincidence detector? 
 (A) X-NOR   (B) NAND 
 (C) X-OR   (D) NOR 
 Ans. (C)  
 
Page 5


AC07/AT07                                                                       Computer Architecture 
 
 
 1 
TYPICAL QUESTIONS & ANSWERS 
PART - I 
OBJECTIVE TYPE QUESTIONS 
Each Question carries 2 marks. 
Choose correct or the best alternative in the following: 
Q.1 In a virtual memory system, the addresses used by the programmer belongs to 
 (A) memory space.               (B) physical addresses.  
 (C) address space.                (D) main memory address. 
  
 Ans: C 
 An address used by programmers in a system supporting virtual memory concept is 
 called virtual address and the set of such addresses are called address space. 
 
Q.2  The method for updating the main memory as soon as a word is removed from the    
  Cache is called 
 (A) Write-through                  (B) write-back  
 (C) protected write                 (D) cache-write 
  
 Ans: B 
 In this method only cache location is updated during write operation. 
 
Q.3 A control character is sent at the beginning as well as at the end of each block in the 
 synchronous-transmission in order to 
 (A) Synchronize the clock of transmitter and receiver. 
 (B) Supply information needed to separate the incoming bits into individual  
        character. 
 (C) Detect the error in transmission and received system. 
 (D) Both (A) and (C). 
  
 Ans B 
 As the data are sent continuously as a block of data at the rate dictated by the clock 
 frequency, so the receiver should be supplied with the same function about the same 
 bit length in order to interrupt the information.  
 
Q.4  In a non-vectored interrupt, the address of interrupt service routine is 
 (A) Obtained from interrupt address table. 
 (B) Supplied by the interrupting I/O device. 
 (C) Obtained through Vector address generator device. 
 (D) Assigned to a fixed memory location. 
  
 Ans: D 
 The source device that interrupted the processor supply the vector address which 
 helps processor to find out the actual memory location where ISR is stored for the 
 device. 
AC07/AT07                                                                       Computer Architecture 
 
 
 2 
Q.5 Divide overflow is generated when 
 (A) Sign of the dividend is different from that of divisor. 
 (B) Sign of the dividend is same as that of divisor. 
 (C) The first part of the dividend is smaller than the divisor. 
 (D) The first part of the dividend is greater than the divisor. 
  
 Ans: B 
 If the first part of the dividend is greater than the deviser, then the result should be 
 of greater length, then that can be hold in a register of the system. The registers are 
 of fixed length in  
 any processor. 
 
Q.6 Which method is used for resolving data dependency conflict by the compiler 
 itself? 
 (A) Delayed load.                 (B) operand forwarding.  
 (C) Pre fetch target instruction.          (D) loop buffer. 
  
 Ans: A 
 In case of delayed load technique the complier detects the data conflict and reorder 
 the instruction as necessary to delay the loading of the conflicting data by inserting 
 no operation instructions. 
 
Q.7  Stack overflow causes  
 (A) Hardware interrupt. 
 (B) External interrupt.  
         (C) Internal interrupt.  
 (D) Software interrupt. 
  
 Ans: C 
 Stack overflow occurs while execution of a program due to logical faults. So it is a 
 program dependent, hence interrupt activated. 
 
Q.8 Arithmetic shift left operation 
 (A) Produces the same result as obtained with logical shift left operation. 
 (B) Causes the sign bit to remain always unchanged. 
 (C) Needs additional hardware to preserve the sign bit. 
 (D) Is not applicable for signed 2's complement representation. 
  
 Ans:  A 
 If the register hold minus five in two’s compliment form than in arithmetic shift left 
 the contents of the register shall be  
                
 It is found that the register contents multiplied by two after logical shift left 
 operation. Hence arithmetic shift left operation is same as logical shift operation. 
 
AC07/AT07                                                                       Computer Architecture 
 
 
 3 
Q.9 Zero address instruction format is used for 
 (A) RISC architecture.      
       (B) CISC architecture. 
 (C) Von-Neuman architecture.  
 (D) Stack-organized architecture. 
  
 Ans: D 
 In stack organized architecture push and pop instruction is needs a address field to 
 specify the location of data for pushing into the stack and destination location 
 during pop operation but for logic and arithmetic operation the instruction does not 
 need any address field as it operates on the top two data available in the stack. 
 
Q.10  Address symbol table is generated by the 
 (A) memory management software. 
 (B) assembler. 
 (C) match logic of associative memory.  
 (D) generated by operating system 
  
 Ans: B 
 During the first pass of assembler address symbol table is generated which contains 
 the label used by the programmer and its actual address with reference to the stored 
 program. 
 
Q.11  The ASCII code for letter A is 
  (A)  1100011   (B)  1000001 
  (C)  1111111   (D)  0010011 
   
  Ans. (B)  
 
Q.12 The simplified expression of (A+B) +  C is 
 (A) (A + B)C  (B) A(B + C) 
 (C) (C+A + B)  (D) None of these 
  
 Ans.  (A) 
   
Q.13 The negative numbers in the binary system can be represented by 
 (A)  Sign magnitude (B) I's complement 
 (C)  2's complement (D) All of the above 
  
 Ans. (C)  
 
Q.14 ABCD - seven segment decoder / driver in connected to an LED display.  
 Which segments are illuminated for the input code DCBA = 0001. 
 (A)b, c    (B) c, b 
 (C)a, b, c   (D) a, b, c, d 
  
 Ans. (A)  
 
Q.15 How many flip-flops are required to produce a divide-by-32 device? 
 (A)4    (B) 6 
AC07/AT07                                                                       Computer Architecture 
 
 
 4 
 (C)5    (D) 7 
  
 Ans. (C)  
 
Q.16 The content of a 4-bit register is initially 1101.  The register is shifted 2 times  to 
 the right with the serial input being 1011101.   
 What is the content of the register after each shift?  
 (A)1110, 0111  (B) 0001, 1000 
 (C)1101, 1011  (D) 1001, 1001 
  
 Ans. (A)  
 
Q.17 How many different addresses are required by the memory that contain 16K 
 words? 
 (A)16,380   (B) 16,382 
 (C)16,384   (D) 16,386 
  
 Ans. (C)  
   
Q.18 What is the bit storage capacity of a ROM with a 512' 4-organization? 
 (A) 2049   (B) 2048 
 (C) 2047   (D) 2046 
  
 Ans. (B)  
 
Q.19 DMA interface unit eliminates the need to use CPU registers to transfer data 
 from 
 (A) MAR to MBR (B) MBR to MAR 
 (C) I/O units to memory (D) Memory to I/O units 
  
 Ans. (D)  
 
Q.20 How many 128 x 8 RAM chips are needed to provide a memory capacity of 
 2048 bytes? 
 (A) 8    (B) 16 
 (C) 24    (D) 32 
  
 Ans.  (B)  
 
Q.21 Which of the following is a self complementing code? 
 (A) 8421 code  (B) 5211 
 (C) Gray code  (D) Binary code 
  
 Ans. (A)   
  
Q.22 Which gate can be used as anti-coincidence detector? 
 (A) X-NOR   (B) NAND 
 (C) X-OR   (D) NOR 
 Ans. (C)  
 
AC07/AT07                                                                       Computer Architecture 
 
 
 5 
Q.23 Which of the following technology can give high speed RAM? 
 (A) TTL   (B) CMOS 
 (C) ECL   (D) NMOS 
  
 Ans. (C)  
 
Q.24 In 8085 microprocessor how many I/O devices can be interfaced in I/O  mapped 
 I/O technique? 
 (A) Either 256 input devices or 256 output devices. 
 (B) 256 I/O devices. 
 (C) 256 input devices & 256 output devices. 
 (D) 512 input-output devices. 
  
 Ans. (C)  
 
Q.25 After reset, CPU begins execution of instruction from memory address 
 (A) 0101
H
  (B) 8000
H
 
 (C) 0000
H
  (D) FFFF
H
 
  
 Ans. (C)  
 
Q.26  Which is true for a typical RISC architecture? 
 (A) Micro programmed control unit. 
 (B) Instruction takes multiple clock cycles.  
 (C) Have few registers in CPU. 
 (D) Emphasis on optimizing instruction pipelines. 
  
 Ans. (A)  
 
Q.27 When an instruction is read from the memory, it is called 
 (A) Memory Read cycle (B) Fetch cycle 
 (C) Instruction cycle (D) Memory write cycle 
  
 Ans. (B)  
   
Q.28 Which activity does not take place during execution cycle? 
 (A) ALU performs the arithmetic & logical operation. 
 (B) Effective address is calculated.   
 (C) Next instruction is fetched. 
 (D) Branch address is calculated & Branching conditions are    
  checked. 
 Ans. (D)  
 
Q.29 A circuit in which connections to both AND and OR arrays can be   
 programmed is called 
 (A) RAM  (B) ROM 
 (C) PAL   (D) PLA 
 Ans. (A)  
 
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