S-R Flip Flops Electrical Engineering (EE) Notes | EduRev

Digital Electronics

Electrical Engineering (EE) : S-R Flip Flops Electrical Engineering (EE) Notes | EduRev

The document S-R Flip Flops Electrical Engineering (EE) Notes | EduRev is a part of the Electrical Engineering (EE) Course Digital Electronics.
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Typical applications for SR Flip-flops.

The basic building bock that makes computer memories possible, and is also used in many sequential logic circuits is the flip-flop or bi-stable circuit. Just two inter-connected logic gates make up the basic form of this circuit whose output has two stable output states. When the circuit is triggered into either one of these states by a suitable input pulse, it will ‘remember’ that state until it is changed by a further input pulse, or until power is removed. For this reason the circuit may also be called a Bi-stable Latch.

The SR flip-flop can be considered as a 1-bit memory, since it stores the input pulse even after it has passed. Flip-flops (or bi-stables) of different types can be made from logic gates and, as with other combinations of logic gates, the NAND and NOR gates are the most versatile, the NAND being most widely used. This is because, as well as being universal, i.e. it can be made to mimic any of the other standard logic functions, it is also cheaper to construct. Other, more widely used types of flip-flop are the JK, the D type and T type, which are developments of the SR flip-flop and will be studied in Modules 5.3 and 5.4. 

 

The SR Flip-flop.

The SR (Set-Reset) flip-flop is one of the simplest sequential circuits and consists of two gates connected as shown in Fig. 5.2.1. Notice that the output of each gate is connected to one of the inputs of the other gate, giving a form of positive feedback or ‘cross-coupling’.

The circuit has two active low inputs marked S and R, ‘NOT’ being indicated by the bar above the letter, as well as two outputs, Q and Q. Table 5.2.1 shows what happens to the Q and Q outputs when a logic 0 is applied to either the S or R inputs.

S-R Flip Flops Electrical Engineering (EE) Notes | EduRev    S-R Flip Flops Electrical Engineering (EE) Notes | EduRev

 

The SR Flip-flop Truth Table (Table 5.2.1)

  1. Q output is set to logic 1 by applying logic 0 to the S-R Flip Flops Electrical Engineering (EE) Notes | EduRev input.
  2. Returning the S input to logic 1 has no effect. The 0 pulse (high-low-high) has been ‘remembered’ by the Q.
  3. Q is reset to 0 by logic 0 applied to the S-R Flip Flops Electrical Engineering (EE) Notes | EduRev input.
  4. As S-R Flip Flops Electrical Engineering (EE) Notes | EduRev returns to logic 1 the 0 on Q is ‘remembered’ by Q.
     

S-R Flip Flops Electrical Engineering (EE) Notes | EduRev

 

Problems with the SR Flip-flop

There are however, some problems with the operation of this most basic of flip-flop circuits. For conditions 1 to 4 in Table 5.2.1, S-R Flip Flops Electrical Engineering (EE) Notes | EduRev is the inverse of Q. However, in row 5 both inputs are 0, which makes both Q and S-R Flip Flops Electrical Engineering (EE) Notes | EduRev = 1, and as they are no longer opposite logic states, although this state is possible, in practical circuits it is ‘not allowed’.

In row 6 both inputs are at logic 1 and the outputs are shown as ‘indeterminate’, this means that although Q and S-R Flip Flops Electrical Engineering (EE) Notes | EduRev will be at opposite logic states it is not certain whether Q will be 1 or 0, Notice however that in the absence of any input pulses, both inputs are normally at logic 1. This is normally OK, as the outputs will be at the state remembered from the last input pulse. The indeterminate or uncertain logic state only occurs if the inputs change from 0,0 to 1,1 together. This should be avoided in normal operation, but is likely to happen when power is first applied. This could lead to uncertain results, but the flip-flop will work normally once an input pulse is applied to either input.

The SR Flip-flop is therefore, a simple 1-bit memory. If the S input is taken to logic 0 then back to logic 1, any further logic 0 pulses at S-R Flip Flops Electrical Engineering (EE) Notes | EduRev will have no effect on the output.

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