The digital signals processed by logic gates need to have fast rising and falling edges. Taking too much time to change logic states, spending too long in the ‘invalid’ zone between states, can cause unreliable logic levels, timing problems and excessive power dissipation, even shortening the life of logic ICs. Standard gate inputs change from 0 to 1 or 1 to 0 at a voltage of about 2.0V. If there is any noise on the input signal, it may be rapidly changing its voltage above and below this level, so causing the gate to rapidly change state if the noise exceeds the noise margin. These rapid and uncertain changes in the gate’s input circuit will also cause the output to oscillate between 1 and 0, transmitting the problem to any subsequent gates in the digital system.
To avoid these problems, gates with Schmitt inputs such as those shown in Fig. 3.4.7 are often used, especially at the input to a system where noise may be expected, as signals arrive from an external source.
Fig. 3.4.7 Schmitt Gates
Schmitt gates use positive feedback, which causes the gate to switch between logic states extremely quickly. They also have a hysteresis effect, which only allows a change of state to occur as the input voltage passes two specific and different voltages, the Positive-going input threshold voltage (VT+) and the Negative-going input threshold voltage (VT-).
As the input voltage passes VT+ during a positive going transition, the gate input changes very rapidly to its high state. It then cannot return to its low state until the input voltage falls to the lower level of VT-.
This action has several beneficial effects on poor input signals, as illustrated in Fig. 3.4.8.
(a) It can be used to change slowly changing signals to square waves having very fast transitions.
(b) Noise can be removed from signals, provided that the amplitude of the noise is not greater than ΔVT.
(c) Slow rise and fall times can be restored to practically instant transitions by feeding the signal through a Schmitt trigger.
Typical Schmitt Hex inverter and Quad NAND gate ICs from the 74 series are illustrated in Fig. 3.4.9.
Fig 3.4.9 Schmitt Input ICs