Sequential Logic Notes | EduRev

: Sequential Logic Notes | EduRev

 Page 1


Copyright © 2007 Elsevier 4-<1> 
Sequential Logic 
•? Verilog uses certain idioms to describe latches, flip-flops and 
FSMs 
•? Other coding styles may simulate correctly but produce 
incorrect hardware 
Page 2


Copyright © 2007 Elsevier 4-<1> 
Sequential Logic 
•? Verilog uses certain idioms to describe latches, flip-flops and 
FSMs 
•? Other coding styles may simulate correctly but produce 
incorrect hardware 
Copyright © 2007 Elsevier 4-<2> 
D Flip-Flop 
module flop(input            clk,  
            input      [3:0] d,  
            output reg [3:0] q); 
  always @ (posedge clk) 
    q <= d;                // pronounced “q gets d” 
endmodule 
Any signal assigned in an always statement must be declared reg.  In 
this case q is declared as reg 
Beware:  A variable declared reg is not necessarily a registered output. 
 We will show examples of this later. 
Note the use of the <= assignment operator 
Page 3


Copyright © 2007 Elsevier 4-<1> 
Sequential Logic 
•? Verilog uses certain idioms to describe latches, flip-flops and 
FSMs 
•? Other coding styles may simulate correctly but produce 
incorrect hardware 
Copyright © 2007 Elsevier 4-<2> 
D Flip-Flop 
module flop(input            clk,  
            input      [3:0] d,  
            output reg [3:0] q); 
  always @ (posedge clk) 
    q <= d;                // pronounced “q gets d” 
endmodule 
Any signal assigned in an always statement must be declared reg.  In 
this case q is declared as reg 
Beware:  A variable declared reg is not necessarily a registered output. 
 We will show examples of this later. 
Note the use of the <= assignment operator 
Copyright © 2007 Elsevier 4-<3> 
module flopr(input            clk, 
             input            reset,  
             input      [3:0] d,  
             output reg [3:0] q); 
  // synchronous reset 
  always @ (posedge clk) 
    if (reset) q <= 4'b0; 
    else       q <= d; 
endmodule 
Resettable D Flip-Flop 
Page 4


Copyright © 2007 Elsevier 4-<1> 
Sequential Logic 
•? Verilog uses certain idioms to describe latches, flip-flops and 
FSMs 
•? Other coding styles may simulate correctly but produce 
incorrect hardware 
Copyright © 2007 Elsevier 4-<2> 
D Flip-Flop 
module flop(input            clk,  
            input      [3:0] d,  
            output reg [3:0] q); 
  always @ (posedge clk) 
    q <= d;                // pronounced “q gets d” 
endmodule 
Any signal assigned in an always statement must be declared reg.  In 
this case q is declared as reg 
Beware:  A variable declared reg is not necessarily a registered output. 
 We will show examples of this later. 
Note the use of the <= assignment operator 
Copyright © 2007 Elsevier 4-<3> 
module flopr(input            clk, 
             input            reset,  
             input      [3:0] d,  
             output reg [3:0] q); 
  // synchronous reset 
  always @ (posedge clk) 
    if (reset) q <= 4'b0; 
    else       q <= d; 
endmodule 
Resettable D Flip-Flop 
Copyright © 2007 Elsevier 4-<4> 
module flopr(input            clk, 
             input            reset,  
             input      [3:0] d,  
             output reg [3:0] q); 
  // asynchronous reset 
  always @ (posedge clk, posedge reset) 
    if (reset) q <= 4'b0; 
    else       q <= d; 
endmodule 
Resettable D Flip-Flop 
Page 5


Copyright © 2007 Elsevier 4-<1> 
Sequential Logic 
•? Verilog uses certain idioms to describe latches, flip-flops and 
FSMs 
•? Other coding styles may simulate correctly but produce 
incorrect hardware 
Copyright © 2007 Elsevier 4-<2> 
D Flip-Flop 
module flop(input            clk,  
            input      [3:0] d,  
            output reg [3:0] q); 
  always @ (posedge clk) 
    q <= d;                // pronounced “q gets d” 
endmodule 
Any signal assigned in an always statement must be declared reg.  In 
this case q is declared as reg 
Beware:  A variable declared reg is not necessarily a registered output. 
 We will show examples of this later. 
Note the use of the <= assignment operator 
Copyright © 2007 Elsevier 4-<3> 
module flopr(input            clk, 
             input            reset,  
             input      [3:0] d,  
             output reg [3:0] q); 
  // synchronous reset 
  always @ (posedge clk) 
    if (reset) q <= 4'b0; 
    else       q <= d; 
endmodule 
Resettable D Flip-Flop 
Copyright © 2007 Elsevier 4-<4> 
module flopr(input            clk, 
             input            reset,  
             input      [3:0] d,  
             output reg [3:0] q); 
  // asynchronous reset 
  always @ (posedge clk, posedge reset) 
    if (reset) q <= 4'b0; 
    else       q <= d; 
endmodule 
Resettable D Flip-Flop 
Copyright © 2007 Elsevier 4-<5> 
module flopren(input            clk, 
               input            reset,  
               input            en,  
               input      [3:0] d,  
               output reg [3:0] q); 
  // asynchronous reset and enable  
  always @ (posedge clk, posedge reset) 
    if      (reset) q <= 4'b0; 
    else if (en)    q <= d; 
endmodule  
D Flip-Flop with Enable 
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