A State Table and Timing Diagram illustrating the operation of Fig.5.7.2 is shown in Fig. 5.7.3 where the timing diagram shows the time relationship between the CK pulses and changes at the Q outputs of the circuit. It can be seen that if the serial input goes from 0 to 1 just before CK pulse 1, the Q output of flip-flop FF0 will go high at the rising edge of CK pulse 1. At the next clock pulse rising edge, the logic 1 will be transferred to FF1 and so on until it reaches FF3, and the serial output.
The same action can also be illustrated by a State Table, which, rather than showing timing data, shows the states of the four Q outputs after each clock pulse. After each CK pulse one more flip-flop output is set to 1 until, after 4 pulses, column 4 shows that all Q outputs, including the serial output, are at logic 1. This form of operation is called ‘serial in/serial out’ or SISO.
Fig. 5.7.3 Timing Diagram and State Table for SISO Operation
In Fig. 5.7.4 the shift register is modified to include additional Q outputs from each flip-flop, so allowing the register to input serial data, and output it in both serial and parallel form. The register could therefore now be called both a ‘Serial In/Serial Out and Serial In/Parallel Out’ (SISO/SIPO) register. This format is the basis for converting serial data to parallel data.
If use is also made of the output, and the additional preset and clear inputs available on many flip-flops, the shift register could be made more versatile still.
Fig. 5.7.5 shows a shift register modified to enable it to be loaded with a 4-bit parallel number, which may then be shifted right to appear at the serial output one bit at a time. As the ‘Parallel In/Serial Out’ or PISO register also has a serial input, it can also be used as a SISO register, and if extra outputs from each Q output were also included, the register would also have Serial In/Parallel Out (SIPO) operation.