System Approach to VLSI Design Electrical Engineering (EE) Notes | EduRev

VLSI System Design

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Electrical Engineering (EE) : System Approach to VLSI Design Electrical Engineering (EE) Notes | EduRev

The document System Approach to VLSI Design Electrical Engineering (EE) Notes | EduRev is a part of the Electrical Engineering (EE) Course VLSI System Design.
All you need of Electrical Engineering (EE) at this link: Electrical Engineering (EE)

Objectives

 In this lecture you will learn the following

  • What is System?
  • Design Abstraction Levels
  • Delay and Interconnect Issues in physical circuits


2.1 What is System?

2.1.1 Definition of System

system is something which gives an output when it is provided with an input (see figure 1).

System Approach to VLSI Design Electrical Engineering (EE) Notes | EduRev

 

 2.1.2 System-on-Chip(SoC)

 

As the name suggests, its basically means shrinking the whole system onto a single chip.The most important feature of the chip is that its functionality should be comparable to that of the original system. It improves quality, productivity and performance.

System Approach to VLSI Design Electrical Engineering (EE) Notes | EduRev


2.2 Design Abstraction levels

Every system should be decomposed into three fundamental domains:

 1. Behavioral Domain

 2. Structural Domain

 3. Physical Domain

In every domain, there are diffirent layers or levels of hierarchy. The following Onion Diagram will give a better understanding of this -

System Approach to VLSI Design Electrical Engineering (EE) Notes | EduRev

Figure 3. Onion Diagram

 We can design the system at various layers, which are called design abstraction levels:

 

 1. Architechture

2. Algorithm

3. Modules (or Functions)

4. Logic

5. Switch

6. Circuit

7. Device


In this course, we are only dealing with Logic, Switch and Circuit levels.

Representation examples

Behavioral Representation

System Approach to VLSI Design Electrical Engineering (EE) Notes | EduRev

Structural Representation

System Approach to VLSI Design Electrical Engineering (EE) Notes | EduRev

 

2.3 Delay and Interconnect Issues in physical circuits

It must be noted that when the adder described (in the above structural Representation) is realized physically, the output may not arrive at the instant the input is given i.e. if the input is given at time t=0, output can be obtained at time t=t1>0, where values of t1may range from picoseconds to milliseconds, but never zero.

System Approach to VLSI Design Electrical Engineering (EE) Notes | EduRev

Figure 4: Delay in system output
These delays may occur in the devices used to realize the system. However, today the major concern of designers are are the interconnecting wires which connect the various devices. They are the major bottleneck in the speed of the systems today. They occur due to parasitic resistances and capicitances present in the circuits designed.

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