Temperature-Aware Design IT & Software Notes | EduRev

IT & Software : Temperature-Aware Design IT & Software Notes | EduRev

 Page 1


Temperature-Aware Design
Presented by Mehul Shah
4/29/04
Page 2


Temperature-Aware Design
Presented by Mehul Shah
4/29/04
The Problem
? Power & Thermal densities are increasing
? Currently @ 50W/cm
2
, 100W/cm
2
@ 50nm technology
? Power density doubles every 3 years
? Operating Vdd scaling much more slowly (ITRS)
? Cost of cooling rising exponentially
? $1 - $3 per Watt of power dissipation
? Packages designed for worst case power
? Hot spots – heat dissipation non-uniform across chip
? Low-Power design techniques not sufficient
? Big Hammer : Global Clock Gating limits performance
Page 3


Temperature-Aware Design
Presented by Mehul Shah
4/29/04
The Problem
? Power & Thermal densities are increasing
? Currently @ 50W/cm
2
, 100W/cm
2
@ 50nm technology
? Power density doubles every 3 years
? Operating Vdd scaling much more slowly (ITRS)
? Cost of cooling rising exponentially
? $1 - $3 per Watt of power dissipation
? Packages designed for worst case power
? Hot spots – heat dissipation non-uniform across chip
? Low-Power design techniques not sufficient
? Big Hammer : Global Clock Gating limits performance
Impact of Temperature on Design
? Increased Delay, Lower Reliability
? Slower Transistors
? Carrier mobility lower at higher temperature
? Inverter 35% slower at 110
o
C vs. 60
o
C
? Higher Leakage Power
? By orders of magnitude at higher temperature
? Leakage becoming more significant than switching power
? Higher Metal Resistivity
? Copper 39% more resistive at 120
o
C vs. 20
o
C
? Lower Mean-Time-To-Failure (MTF)
? MTF = MTF
o
exp (E
a
/ k
b
T)
? MTF decreases exponentially w/ Temperature
Page 4


Temperature-Aware Design
Presented by Mehul Shah
4/29/04
The Problem
? Power & Thermal densities are increasing
? Currently @ 50W/cm
2
, 100W/cm
2
@ 50nm technology
? Power density doubles every 3 years
? Operating Vdd scaling much more slowly (ITRS)
? Cost of cooling rising exponentially
? $1 - $3 per Watt of power dissipation
? Packages designed for worst case power
? Hot spots – heat dissipation non-uniform across chip
? Low-Power design techniques not sufficient
? Big Hammer : Global Clock Gating limits performance
Impact of Temperature on Design
? Increased Delay, Lower Reliability
? Slower Transistors
? Carrier mobility lower at higher temperature
? Inverter 35% slower at 110
o
C vs. 60
o
C
? Higher Leakage Power
? By orders of magnitude at higher temperature
? Leakage becoming more significant than switching power
? Higher Metal Resistivity
? Copper 39% more resistive at 120
o
C vs. 20
o
C
? Lower Mean-Time-To-Failure (MTF)
? MTF = MTF
o
exp (E
a
/ k
b
T)
? MTF decreases exponentially w/ Temperature
Moral of the Story
? Problem: Temperature adversely affects power, performance & 
reliability
? Solution: “Temperature-Aware” Design
Page 5


Temperature-Aware Design
Presented by Mehul Shah
4/29/04
The Problem
? Power & Thermal densities are increasing
? Currently @ 50W/cm
2
, 100W/cm
2
@ 50nm technology
? Power density doubles every 3 years
? Operating Vdd scaling much more slowly (ITRS)
? Cost of cooling rising exponentially
? $1 - $3 per Watt of power dissipation
? Packages designed for worst case power
? Hot spots – heat dissipation non-uniform across chip
? Low-Power design techniques not sufficient
? Big Hammer : Global Clock Gating limits performance
Impact of Temperature on Design
? Increased Delay, Lower Reliability
? Slower Transistors
? Carrier mobility lower at higher temperature
? Inverter 35% slower at 110
o
C vs. 60
o
C
? Higher Leakage Power
? By orders of magnitude at higher temperature
? Leakage becoming more significant than switching power
? Higher Metal Resistivity
? Copper 39% more resistive at 120
o
C vs. 20
o
C
? Lower Mean-Time-To-Failure (MTF)
? MTF = MTF
o
exp (E
a
/ k
b
T)
? MTF decreases exponentially w/ Temperature
Moral of the Story
? Problem: Temperature adversely affects power, performance & 
reliability
? Solution: “Temperature-Aware” Design
Temperature Aware Design
? Thermal Modeling
? Estimate Operating Temperature
? Simple : Allow architects to easily reason about 
thermal effects
? Detailed : Model runtime temperature at 
Functional-Unit granularity
? Computationally Efficient
? Flexible : Easily extend to novel architectures
? Dynamic Thermal Management
? Use runtime behavior and thermal status to 
adjust/distribute workload among Functional-Units
Read More
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