Toggle flip-flops are the basic components of digital counters, and all of the D type devices are adaptable for such use. When an electronic counter is used for counting, what are actually being counted are pulses appearing at the CK input, which may be either regular pulses derived from an internal clock, or they can be irregular pulses generated by some external event.
When a toggle flip-flop is used as one stage of a counter, its Q output changes to the opposite state, (it toggles) high or low on each clock pulse. Most edge-triggered flip-flops can be used as toggle flip-flops including the D type, which can be converted to a toggle flip-flop with a simple modification. In theory all that is necessary to convert an edge triggered D Type to a T type is to connect the Q output directly to the D input as shown in Fig. 5.3.8. The actual input is now CK. The effect of this mode of operation is also shown in the timing diagram in Fig. 5.3.8 using a positive edge triggered D type flip-flop.
Suppose that initially CK and Q = 0. Then and D must be 1. At the rising edge of a CK pulse, the logic 1 at D is allowed into the flip-flop and, at the end of the flip-flop’s propagation delay, appears at Q, and changes to logic 0 at the same time.
This logic 0 is now fed back to D, but it is important that it is not immediately accepted into the D input, otherwise oscillation could occur with D continually changing between 1 and 0. However, because of the flip-flop’s propagation delay, when the logic 0 from arrives at D, the very short edge-triggering period will have completed, and the change in data at D will be ignored.
At the next CK rising edge of the clock signal, the 0 at D now passes to Q, making and D logic 1 again. The Q output of the flip-flop therefore toggles at each positive going edge of the CK pulse.
Because the Q output changes state at each clock pulse rising edge, the 0 period and the 1 period of the Q output will always be of equal length, and the output will be a square wave with a 1:1 mark to space ratio, its frequency will be half that of CK.
To use toggle flip-flops as simple binary counters, a number of toggle flip-flops may be connected in cascade, with the Q output of the first flip-flop in the series, being connected to the CK input of the next flip-flop and so on. This is also the principle of frequency division. Exactly how counters and dividers can be constructed from toggle flip-flops is explained in Sequential Logic Module 5.6
In practice however, using direct feedback from to D can cause problems as, to ensure stable operation and avoid unwanted oscillation, it is important in any digital circuit, that any changes in logic level taking place at D must be both stable, (free from any overshoot or ringing etc.) and at a valid logic level during a short period, before and after the clock signal causes a change. These periods are called the set up and hold times.
Although it is easy to think of the clock signal initiating a change at a particular time, e.g. when its rising edge occurs, data is actually clocked into input D when the CK waveform reaches a certain voltage level. In 74HC series gates this level is 50% of VDD, as illustrated in Fig 5.3.9. This shows in expanded time detail, the transitions taking place at the D and CK inputs of a D type positive edge triggered flip-flop.
To guarantee correct triggering, it is important that the data at the D input has settled at a valid logic level before the clock signal triggers any change. Therefore there must be some time allowed from when the D input first becomes valid to allow time for any slow rising pulse, any overshoot or ringing to occur before the clock pulse samples the logic level.
For example, the time between point (a) in Fig.5.3.9, where D initially falls below 50% of VDD and the time when CK rises to its trigger threshold of 50% VDD (point b) is called the set up time (tsetup or tsu), and in 74HC series ICs this will typically be between 5ns and 15ns.
After the trigger point there must be a further period (b to c in Fig. 5.3.9) where the data at D must remain at the same valid logic level to ensure that the correct logic level has been accepted. This is called the hold time (thold or th) and is typically around 3ns in 74HC series ICs.
In sequential logic circuits, precise timing is vitally important. The design of a circuit must take into consideration not only set up and hold times but also the propagation times of gates or flip-flops in each path that a digital signal takes through a circuit. Failure to get the timing right can lead to problems such as ‘glitches’ i.e. sudden sharp spikes, as a device such as a flip-flop momentarily produces a change from one logic level to another and back again. Such glitches may be very short (a few nanoseconds) but sufficient to trigger another device to a wrong logic level.
With devices such as flip-flops using both triggering and feedback, incorrect timing can also lead to instability and unwanted oscillations. Avoiding such problems is a major reason for the use of edge triggering and master slave devices.
A selection of D type Flip-flop ICs are listed below.