Computer Organisation Notes - Computer Science Engineering (CSE)

 Page 1


R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Page 2


R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
COMPUTER ORGANIZATION 
R 402            2+1+0 
 
Module 1 
Introduction: Organization and Architecture – Review of basic operational 
concepts – CPU- single bus and two bus organization, Execution of a complete 
instruction – interconnection structures – layered view of a computer system. 
 
Module 2 
CPU - Arithmetic: Signed addition and subtraction – serial and parallel adder – 
BCD adder – Carry look ahead adder, Multiplication – Array multiplier – Booth‘s 
Algorithm, Division – Restoring and non-restoring division, floating point 
arithmetic - ALU Design. 
 
Module 3 
Control Unit Organization: Processor Logic Design – Processor Organization – 
Control Logic Design – Control Organization – Hardwared control – 
Microprogram control – PLA control – Microprogram sequencer, Horizontal and 
vertical micro instructions – Nano instructions. 
 
Module 4 
Memory:  Memory hierarchy – RAM and ROM – Memory system considerations 
– Associative memory, Virtual memory – Cache memory – Memory interleaving. 
 
Module 5 
Input – Output:  Printers, Plotters, Displays, Keyboard, Mouse, OMR and OCR, 
Device interface – I/O processor – Standard I/O interfaces – RS 232 C, IEEE 
488.2 (GPIB). 
  
 
References 
 
1. Computer Organization - Hamacher, Vranesic and Zaky, Mc Graw Hill 
2. Digital Logic and Computer Design - Morris Mano, PHI  
3. Computer Organization and Architecture  -William Stallings, Pearson Education 
Asia. 
4. Computer Organization and Design - Pal Chaudhuri, PHI 
5. Computer Organization and Architecture -M Morris Mano, PHI 
6. Computer Architecture and Organization - John P Hayes, Mc Graw Hill 
 
 
 
 
 
 
 
Page 3


R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
COMPUTER ORGANIZATION 
R 402            2+1+0 
 
Module 1 
Introduction: Organization and Architecture – Review of basic operational 
concepts – CPU- single bus and two bus organization, Execution of a complete 
instruction – interconnection structures – layered view of a computer system. 
 
Module 2 
CPU - Arithmetic: Signed addition and subtraction – serial and parallel adder – 
BCD adder – Carry look ahead adder, Multiplication – Array multiplier – Booth‘s 
Algorithm, Division – Restoring and non-restoring division, floating point 
arithmetic - ALU Design. 
 
Module 3 
Control Unit Organization: Processor Logic Design – Processor Organization – 
Control Logic Design – Control Organization – Hardwared control – 
Microprogram control – PLA control – Microprogram sequencer, Horizontal and 
vertical micro instructions – Nano instructions. 
 
Module 4 
Memory:  Memory hierarchy – RAM and ROM – Memory system considerations 
– Associative memory, Virtual memory – Cache memory – Memory interleaving. 
 
Module 5 
Input – Output:  Printers, Plotters, Displays, Keyboard, Mouse, OMR and OCR, 
Device interface – I/O processor – Standard I/O interfaces – RS 232 C, IEEE 
488.2 (GPIB). 
  
 
References 
 
1. Computer Organization - Hamacher, Vranesic and Zaky, Mc Graw Hill 
2. Digital Logic and Computer Design - Morris Mano, PHI  
3. Computer Organization and Architecture  -William Stallings, Pearson Education 
Asia. 
4. Computer Organization and Design - Pal Chaudhuri, PHI 
5. Computer Organization and Architecture -M Morris Mano, PHI 
6. Computer Architecture and Organization - John P Hayes, Mc Graw Hill 
 
 
 
 
 
 
 
R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
 
1.1 Introduction to Computer organization and architecture 
In describing computer system, a distinction is often made between computer architecture 
and computer organization. 
 
Computer architecture refers to those attributes of a system visible to a programmer, or 
put another way, those attributes that have a direct impact on the logical execution of a 
program. 
Computer organization refers to the operational units and their interconnection that 
realize the architecture specification.  
 
Examples of architecture attributes include the instruction set, the number of bit to 
represent various data types (e.g.., numbers, and characters), I/O mechanisms, and 
technique for addressing memory.  
 
Examples of organization attributes include those hardware details transparent to the 
programmer, such as control signals, interfaces between the computer and peripherals, 
and the memory technology used. 
 
As an example, it is an architectural design issue whether a computer will have a multiply 
instruction. It is an organizational issue whether that instruction will be implemented by a 
special multiply unit or by a mechanism that makes repeated use of the add unit of the 
system. The organization decision may be bases on the anticipated frequency of use of 
the multiply instruction, the relative speed of the two approaches, and the cost and 
physical size of a special multiply unit. 
 
Historically, and still today, the distinction between architecture and organization has 
been an important one. Many computer manufacturers offer a family of computer model, 
all with the same architecture but with differences in organization. Consequently, the 
different models in the family have different price and performance characteristics. 
Furthermore, an architecture may survive many years, but its organization changes with 
changing technology. 
 
Basic Structure of a Computer 
Figure 1 shows the general structure of the IAS computer. It consists of: 
 A main memory, which stores both data and instructions. 
 An arithmetic-logical unit (ALU) capable of operating on binary data. 
 A control unit, which interprets the instructions in memory and causes them to be 
executed. 
 Input and output (I/O) equipment operated by the control unit. 
 
Page 4


R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
COMPUTER ORGANIZATION 
R 402            2+1+0 
 
Module 1 
Introduction: Organization and Architecture – Review of basic operational 
concepts – CPU- single bus and two bus organization, Execution of a complete 
instruction – interconnection structures – layered view of a computer system. 
 
Module 2 
CPU - Arithmetic: Signed addition and subtraction – serial and parallel adder – 
BCD adder – Carry look ahead adder, Multiplication – Array multiplier – Booth‘s 
Algorithm, Division – Restoring and non-restoring division, floating point 
arithmetic - ALU Design. 
 
Module 3 
Control Unit Organization: Processor Logic Design – Processor Organization – 
Control Logic Design – Control Organization – Hardwared control – 
Microprogram control – PLA control – Microprogram sequencer, Horizontal and 
vertical micro instructions – Nano instructions. 
 
Module 4 
Memory:  Memory hierarchy – RAM and ROM – Memory system considerations 
– Associative memory, Virtual memory – Cache memory – Memory interleaving. 
 
Module 5 
Input – Output:  Printers, Plotters, Displays, Keyboard, Mouse, OMR and OCR, 
Device interface – I/O processor – Standard I/O interfaces – RS 232 C, IEEE 
488.2 (GPIB). 
  
 
References 
 
1. Computer Organization - Hamacher, Vranesic and Zaky, Mc Graw Hill 
2. Digital Logic and Computer Design - Morris Mano, PHI  
3. Computer Organization and Architecture  -William Stallings, Pearson Education 
Asia. 
4. Computer Organization and Design - Pal Chaudhuri, PHI 
5. Computer Organization and Architecture -M Morris Mano, PHI 
6. Computer Architecture and Organization - John P Hayes, Mc Graw Hill 
 
 
 
 
 
 
 
R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
 
1.1 Introduction to Computer organization and architecture 
In describing computer system, a distinction is often made between computer architecture 
and computer organization. 
 
Computer architecture refers to those attributes of a system visible to a programmer, or 
put another way, those attributes that have a direct impact on the logical execution of a 
program. 
Computer organization refers to the operational units and their interconnection that 
realize the architecture specification.  
 
Examples of architecture attributes include the instruction set, the number of bit to 
represent various data types (e.g.., numbers, and characters), I/O mechanisms, and 
technique for addressing memory.  
 
Examples of organization attributes include those hardware details transparent to the 
programmer, such as control signals, interfaces between the computer and peripherals, 
and the memory technology used. 
 
As an example, it is an architectural design issue whether a computer will have a multiply 
instruction. It is an organizational issue whether that instruction will be implemented by a 
special multiply unit or by a mechanism that makes repeated use of the add unit of the 
system. The organization decision may be bases on the anticipated frequency of use of 
the multiply instruction, the relative speed of the two approaches, and the cost and 
physical size of a special multiply unit. 
 
Historically, and still today, the distinction between architecture and organization has 
been an important one. Many computer manufacturers offer a family of computer model, 
all with the same architecture but with differences in organization. Consequently, the 
different models in the family have different price and performance characteristics. 
Furthermore, an architecture may survive many years, but its organization changes with 
changing technology. 
 
Basic Structure of a Computer 
Figure 1 shows the general structure of the IAS computer. It consists of: 
 A main memory, which stores both data and instructions. 
 An arithmetic-logical unit (ALU) capable of operating on binary data. 
 A control unit, which interprets the instructions in memory and causes them to be 
executed. 
 Input and output (I/O) equipment operated by the control unit. 
 
R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
 
           Fig.1 Basic structure of a computer. 
1.2 Review of basic operational concepts 
Now we focus on the processing unit, which executes machine instructions and 
coordinates the activities of other units. This unit is often called the instruction Set 
Processor (ISP), or simply the processor. We examine its internal structure and how it 
performs the tasks of fetching, decoding, and executing instructions of a program. The 
processing unit used to be called the central processing unit (CPU). The term ?central? is 
less appropriate today because many modern computer systems include several 
processing units.  
The organization of processors has evolved over the years, driven by developments in 
technology and the need to provide high performance. A common strategy in the 
development of high-performance processors is to make various functional units operate 
in parallel as much as possible. High-performance processors have a pipelined 
organization where the execution of one instruction is started before the execution of the 
preceding instruction is completed. In another approach, known as superscalar operation, 
several instructions are fetched and executed at the same time. Pipelining and superscalar 
architectures are discussed later.  
A typical computing task consists of a series of steps specified by a sequence of machine 
instructions that constitute a program. An instruction is executed by carrying out a 
sequence of more rudimentary operations. These operations and the means by which they 
are controlled are the main topic of this chapter.  
1.3 CPU- single bus organization  
To execute a program, the processor fetches one instruction at a time and performs the 
operations specified. Instructions are fetched from successive memory locations until a 
branch or a jump instruction is encountered. The processor keeps track of the address of 
the memory location containing the next instruction to be fetched using the program 
counter, PC. After fetching an instruction, the contents of the PC are updated to point to 
the next instruction in the sequence. A branch instruction may load a different value into 
the PC.  
Another key register in the processor is the instruction register, IR. Suppose that  
each instruction comprises 4 bytes, and that it is stored in one memory word. To execute  
an instruction, the processor has to perform the following three steps:  
Page 5


R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
COMPUTER ORGANIZATION 
R 402            2+1+0 
 
Module 1 
Introduction: Organization and Architecture – Review of basic operational 
concepts – CPU- single bus and two bus organization, Execution of a complete 
instruction – interconnection structures – layered view of a computer system. 
 
Module 2 
CPU - Arithmetic: Signed addition and subtraction – serial and parallel adder – 
BCD adder – Carry look ahead adder, Multiplication – Array multiplier – Booth‘s 
Algorithm, Division – Restoring and non-restoring division, floating point 
arithmetic - ALU Design. 
 
Module 3 
Control Unit Organization: Processor Logic Design – Processor Organization – 
Control Logic Design – Control Organization – Hardwared control – 
Microprogram control – PLA control – Microprogram sequencer, Horizontal and 
vertical micro instructions – Nano instructions. 
 
Module 4 
Memory:  Memory hierarchy – RAM and ROM – Memory system considerations 
– Associative memory, Virtual memory – Cache memory – Memory interleaving. 
 
Module 5 
Input – Output:  Printers, Plotters, Displays, Keyboard, Mouse, OMR and OCR, 
Device interface – I/O processor – Standard I/O interfaces – RS 232 C, IEEE 
488.2 (GPIB). 
  
 
References 
 
1. Computer Organization - Hamacher, Vranesic and Zaky, Mc Graw Hill 
2. Digital Logic and Computer Design - Morris Mano, PHI  
3. Computer Organization and Architecture  -William Stallings, Pearson Education 
Asia. 
4. Computer Organization and Design - Pal Chaudhuri, PHI 
5. Computer Organization and Architecture -M Morris Mano, PHI 
6. Computer Architecture and Organization - John P Hayes, Mc Graw Hill 
 
 
 
 
 
 
 
R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
 
1.1 Introduction to Computer organization and architecture 
In describing computer system, a distinction is often made between computer architecture 
and computer organization. 
 
Computer architecture refers to those attributes of a system visible to a programmer, or 
put another way, those attributes that have a direct impact on the logical execution of a 
program. 
Computer organization refers to the operational units and their interconnection that 
realize the architecture specification.  
 
Examples of architecture attributes include the instruction set, the number of bit to 
represent various data types (e.g.., numbers, and characters), I/O mechanisms, and 
technique for addressing memory.  
 
Examples of organization attributes include those hardware details transparent to the 
programmer, such as control signals, interfaces between the computer and peripherals, 
and the memory technology used. 
 
As an example, it is an architectural design issue whether a computer will have a multiply 
instruction. It is an organizational issue whether that instruction will be implemented by a 
special multiply unit or by a mechanism that makes repeated use of the add unit of the 
system. The organization decision may be bases on the anticipated frequency of use of 
the multiply instruction, the relative speed of the two approaches, and the cost and 
physical size of a special multiply unit. 
 
Historically, and still today, the distinction between architecture and organization has 
been an important one. Many computer manufacturers offer a family of computer model, 
all with the same architecture but with differences in organization. Consequently, the 
different models in the family have different price and performance characteristics. 
Furthermore, an architecture may survive many years, but its organization changes with 
changing technology. 
 
Basic Structure of a Computer 
Figure 1 shows the general structure of the IAS computer. It consists of: 
 A main memory, which stores both data and instructions. 
 An arithmetic-logical unit (ALU) capable of operating on binary data. 
 A control unit, which interprets the instructions in memory and causes them to be 
executed. 
 Input and output (I/O) equipment operated by the control unit. 
 
R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
 
           Fig.1 Basic structure of a computer. 
1.2 Review of basic operational concepts 
Now we focus on the processing unit, which executes machine instructions and 
coordinates the activities of other units. This unit is often called the instruction Set 
Processor (ISP), or simply the processor. We examine its internal structure and how it 
performs the tasks of fetching, decoding, and executing instructions of a program. The 
processing unit used to be called the central processing unit (CPU). The term ?central? is 
less appropriate today because many modern computer systems include several 
processing units.  
The organization of processors has evolved over the years, driven by developments in 
technology and the need to provide high performance. A common strategy in the 
development of high-performance processors is to make various functional units operate 
in parallel as much as possible. High-performance processors have a pipelined 
organization where the execution of one instruction is started before the execution of the 
preceding instruction is completed. In another approach, known as superscalar operation, 
several instructions are fetched and executed at the same time. Pipelining and superscalar 
architectures are discussed later.  
A typical computing task consists of a series of steps specified by a sequence of machine 
instructions that constitute a program. An instruction is executed by carrying out a 
sequence of more rudimentary operations. These operations and the means by which they 
are controlled are the main topic of this chapter.  
1.3 CPU- single bus organization  
To execute a program, the processor fetches one instruction at a time and performs the 
operations specified. Instructions are fetched from successive memory locations until a 
branch or a jump instruction is encountered. The processor keeps track of the address of 
the memory location containing the next instruction to be fetched using the program 
counter, PC. After fetching an instruction, the contents of the PC are updated to point to 
the next instruction in the sequence. A branch instruction may load a different value into 
the PC.  
Another key register in the processor is the instruction register, IR. Suppose that  
each instruction comprises 4 bytes, and that it is stored in one memory word. To execute  
an instruction, the processor has to perform the following three steps:  
R 402                                                                                    Computer Organization 
 
Computer Science & Engineering Dept.  SJCET, Palai 
 
I. Fetch the contents of the memory location pointed to by the PC. The contents of this 
location are interpreted as an instruction to be executed. Hence, they are loaded into the 
IR. Symbolically, this can be written as  
IR ? [[PC]]  
2. Assuming that the memory is byte addressable, increment the contents of the PC by 4, 
that is,  
            PC ? [PC] +4  
3. Carry out the actions specified by the instruction in the IR.  
In cases where an instruction occupies more than one word, steps I and 2 must be 
repeated as many times as necessary to fetch the complete instruction. These two steps 
are usually referred to as the fetch phase; step 3 constitutes the execution phase.  
To study these operations in detail, we first need to examine the internal organization  
of the processor. They can be organized and interconnected in a variety of ways. We will 
start with a very simple organization. Later in this chapter and in Chapter 8 we will 
present more  
complex structures that provide high performance. Figure 1.1 shows an organization in 
which the arithmetic and logic unit (ALU) and all the registers are interconnected via a 
single common bus. This bus is internal to the processor and should not be confused with 
the external bus that connects the processor to the memory and 110 devices.  
The data and address lines of the external memory bus are shown in Figure 1.1 connected 
to the internal processor bus via the memory data register, MDR, and the memory address 
register, MAR, respectively. Register MDR has two inputs and two outputs. Data may be 
loaded into MDR either from the memory bus or from the internal processor bus. The 
data stored in MDR may be placed on either bus. The input of MAR is connected to the 
internal bus, and its output is connected to the external bus. The control lines of the 
memory bus are connected to the instruction decoder and control logic block. This unit is 
responsible for issuing the signals that control the operation of all the units inside the 
processor and for interacting with the memory bus.  
The number and use of the processor registers R0 through R(n - 1) vary considerably 
from one processor to another. Registers may be provided for general-purpose use by the 
programmer. Some may be dedicated as special-purpose registers, such as index registers 
or stack pointers. Three registers, Y, Z, and TEMP in Figure 1.1, have not been 
mentioned before. These registers are transparent to the programmer, that is, the 
programmer need not be concerned with them because they are never referenced 
explicitly by any instruction. They are used by the processor for temporary storage during 
execution of some instructions. These registers are never used for storing data generated 
by one instruction for later use by another instruction. 
The multiplexer MUX selects either the output of register Y or a constant value 4 to be 
provided as input A of the ALU. The constant 4 is used to increment the contents of the 
program counter. We will refer to the two possible values of the MUX control input 
Select as Select4 and SelectY for selecting the constant 4 or register Y, respectively. 
As instruction execution progresses, data are transferred from one register to another, 
often passing through the ALU to perform some arithmetic or logic operation. The 
instruction decoder and control logic unit is responsible for implementing the actions 
specified by the instruction loaded in the JR register. The decoder generates the control