Interfacing Bus, Protocols, ISA Bus, etc - 1 | Embedded Systems (Web) - Computer Science Engineering (CSE) PDF Download

Instructional Objectives 

After going through this lesson the student would learn 

• Bus, Wires and Ports 
• Basic Protocols of data transfer Bus arbitration 
• ISA bus signals and handshaking 
• Memory mapped I/O and simple I/O 
• Parallel I/O and Port Based I/O 
• Example of interfacing memory to the ports of 8051 

Pre-Requisite 

Digital Electronics, Microprocessors 

Introduction 

The traditional definition of input-output is the devices those create a medium of interaction with the human users. They fall into the following categories such as: 

1. Printers
 2. Visual Display Units
 3. Keyboard
 4. Cameras
 5. Plotters
 6. Scanners 

However in Real-Time embedded systems the definition of I/O devices is very different. An embedded controller needs to communicate with a wide range of devices namely 

1. Analog to Digital (A-D) and Digital to Analog (D-A) Converters
 2. CODECs
 3. Small Screen Displays such as TFT, LCD etc
 4. Antennas
 5. Cameras
 6. Microphones
 7. Touch Screens 

Etc. 

A typical Embedded system is a Digital Camera as shown in Fig. 13.1. As it can be seen it possesses broad range of input-output devices such as Lens, Microphone, speakers, Serial interface standards, TFT screens etc. 

The functionality of an Embedded System can be broadly classified as 

Processing 

• Transformation of data 
• Implemented using processors 

Storage  

• Retention of data 
• Implemented using memory 

And Communication (also called Interfacing) 

• Transfer of data between processors and memories
• Implemented using buses 

Interfacing 

Interfacing is a way to communicate and transfer information in either way without ending into deadlocks. In our context it is a way of effective communication in real time.

This involves 

– Addressing 
 – Arbitration 
 – Protocols 

Fig. 13.2(a) The Bus structure 

Addressing: The data sent by the master over a specified set of lines which enables just the device for which it is meant 

Protocols: The literal meaning of protocol is a set of rules. Here it is a set of formal rules describing how to transfer data, especially between two devices.  

A simple example is memory read and write protocol. The set of rules or the protocol is For read (Fig. 13.2 (b)) 

The CPU must send the memory address
 The read line must be enabled
 The processor must wait till the memory is ready  
 Then accept the bits in the data lines 

Fig. 13.2(b)

For write (Fig. 13.2(c))
 The CPU must send the memory address
 The write line must be enabled
 The processor sends the data over the data lines
 The processor must wait till the memory is ready  

Fig. 13.2(c) 

Arbitration: When the same set of address/data/control lines are shared by different units then the bus arbitration logic comes into play. Access to a bus is arbitrated by a bus master. Each node on a bus has a bus master which requests access to the bus, called a bus request, when then node requires to use the bus. This is a global request sent to all nodes on the bus. The node that currently has access to the bus responds with either a bus grant or a bus busy signal, which is also globally known to all bus masters. (Fig. 13.3) 

Fig. 13.3 The bus arbitration of the DMA, known as direct memory access controller which is responsible for transferring data between an I/O device and memory without involving the CPU. It starts with a bus request to the CPU and after it is granted it takes over the address/data and control bus to initiate the data transfer. After the data transfer is complete it passes the control over to the CPU. 

Before learning more details about each of these concepts a concrete definition of the following terms is necessary. 

Wire: It is just a passive physical connection with least resistance 

Bus: A group of signals (such as data, address etc). It may be augmented with buffers latches etc. A bus has standard specification such as number of bits, the clock speed etc. 

Port: It is the set of physical wires available so that any device which meets the specified standard can be directly plugged in. Example is the serial, parallel and USB port of the PC. 

Time multiplexing: This is to Share a single set of wires for multiple pieces of data. It saves wires at expense of time 

The Handshaking Protocol 

Strobe  Protocol 

Fig. 13.5(a) Strobe Protocol 

1. Master asserts req to receive data
 2. Servant puts data on bus within time taccess
 3. Master receives data and deasserts req
 4. Servant ready for next request 

Handshake Protocol 

Fig. 13.5(b) Handshake Protocol 

1. Master asserts req to receive data
 2. Servant puts data on bus and asserts ack
 3. Master receives data and deasserts req
 4. Servant ready for next request 

The Strobe & Handshake combined 

Fig. 13.5(c) Strobe and Handshake Combined

Handshaking Example in ISA Bus 

The Industry Standard Architecture (ISA Bus) has been described as below This is a standard bus architecture developed to help the various designers to customize their product and the interfaces. The pin configuration and the signals are discussed below. 

ISA Signal Descriptions 

SA19 to SA0 (SA for System Address)  

System Address bits 19:0 are used to address memory and I/O devices within the system. These signals may be used along with LA23 to LA17 to address up to 16 megabytes of memory. Only the lower 16 bits are used during I/O operations to address up to 64K I/O locations. SA19 is the most significant bit. SA0 is the least significant bit. These signals are gated on the system bus when BALE is high and are latched on the falling edge of BALE. They remain valid throughout a read or write command. These signals are normally driven by the system microprocessor or DMA controller, but may also be driven by a bus master on an ISA board that takes ownership of the bus.  

LA23 to LA17

Unlatched Address bits 23:17 are used to address memory within the system. They are used along with SA19 to SA0 to address up to 16 megabytes of memory. These signals are valid when BALE is high. They are "unlatched" and do not stay valid for the entire bus cycle. Decodes of these signals should be latched on the falling edge of BALE.  

AEN  

Address Enable is used to degate the system microprocessor and other devices from the bus during DMA transfers. When this signal is active the system DMA controller has control of the address, data, and read/write signals. This signal should be included as part of ISA board select decodes to prevent incorrect board selects during DMA cycles.  

BALE  

Buffered Address Latch Enable is used to latch the LA23 to LA17 signals or decodes of these signals. Addresses are latched on the falling edge of BALE. It is forced high during DMA cycles. When used with AEN, it indicates a valid microprocessor or DMA address. 

CLK  

System Clock is a free running clock typically in the 8MHz to 10MHz range, although its exact frequency is not guaranteed. It is used in some ISA board applications to allow synchronization with the system microprocessor. 

SD15 to SD0  

System Data serves as the data bus bits for devices on the ISA bus. SD15 is the most significant bit. SD0 is the least significant bits. SD7 to SD0 are used for transfer of data with 8-bit devices. SD15 to SD0 are used for transfer of data with 16-bit devices. 16-bit devices transferring data with 8-bit devices shall convert the transfer into two 8-bit cycles using SD7 to SD0.  

DACK0 to DACK3 and DACK5 to DACK7  

DMA Acknowledge 0 to 3 and 5 to 7 are used to acknowledge DMA requests on DRQ0 to DRQ3 and DRQ5 to DRQ7.  

DRQ0 to DRQ3 and DRQ5 to DRQ7  

DMA Requests are used by ISA boards to request service from the system DMA controller or to request ownership of the bus as a bus master device. These signals may be asserted asynchronously. The requesting device must hold the request signal active until the system board asserts the corresponding DACK signal.  

I/O CH CK  

I/O Channel Check signal may be activated by ISA boards to request than an non-maskable interrupt (NMI) be generated to the system microprocessor. It is driven active to indicate a uncorrectable error has been detected. 

I/O CH RDY 

I/O Channel Ready allow slower ISA boards to lengthen I/O or memory cycles by inserting wait states. This signals normal state is active high (ready). ISA boards drive the signal inactive low (not ready) to insert wait states. Devices using this signal to insert wait states should drive it low immediately after detecting a valid address decode and an active read or write command. The signal is release high when the device is ready to complete the cycle.

IOR 

I/O Read is driven by the owner of the bus and instructs the selected I/O device to drive read data onto the data bus.

IOW  

I/O Write is driven by the owner of the bus and instructs the selected I/O device to capture the write data on the data bus.    

IRQ3 to IRQ7 and IRQ9 to IRQ12 and IRQ14 to IRQ15  

Interrupt Requests are used to signal the system microprocessor that an ISA board requires attention. An interrupt request is generated when an IRQ line is raised from low to high. The line must be held high until the microprocessor acknowledges the request through its interrupt service routine. These signals are prioritized with IRQ9 to IRQ12 and IRQ14 to IRQ15 having the highest priority (IRQ9 is the highest) and IRQ3 to IRQ 7 have the lowest priority (IRQ7 is the lowest). 

SMEMR  

System Memory Read instructs a selected memory device to drive data onto the data bus. It is active only when the memory decode is within the low 1 megabyte of memory space. SMEMR is derived from MEMR and a decode of the low 1 megabyte of memory. 

SMEMW  

System Memory Write instructs a selected memory device to store the data currently on the data bus. It is active only when the memory decode is within the low 1 megabyte of memory space. SMEMW is derived from MEMW and a decode of the low 1 megabyte of memory. 

MEMR 

Memory Read instructs a selected memory device to drive data onto the data bus. It is active on all memory read cycles.  

MEMW  

Memory Write instructs a selected memory device to store the data currently on the data bus. It is active on all memory write cycles.  

REFRESH 

Memory Refresh is driven low to indicate a memory refresh operation is in progress.  

OSC  

Oscillator is a clock with a 70ns period (14.31818 MHz). This signal is not synchronous with the system clock (CLK).  

RESET DRV  

Reset Drive is driven high to reset or initialize system logic upon power up or subsequent system reset.  

TC 

Terminal Count provides a pulse to signal a terminal count has been reached on a DMA channel operation. 

MASTER 

Master is used by an ISA board along with a DRQ line to gain ownership of the ISA bus. Upon receiving a -DACK a device can pull -MASTER low which will allow it to control the system address, data, and control lines. After MASTER is low, the device should wait one CLK period before driving the address and data lines, and two clock periods before issuing a read or write command.

MEM CS16 

Memory Chip Select 16 is driven low by a memory slave device to indicate it is capable of performing a 16-bit memory data transfer. This signal is driven from a decode of the LA23 to LA17 address lines.  

I/O CS16  

I/O Chip Select 16 is driven low by a I/O slave device to indicate it is capable of performing a 16-bit I/O data transfer. This signal is driven from a decode of the SA15 to SA0 address lines.  

0WS 

Zero Wait State is driven low by a bus slave device to indicate it is capable of performing a bus cycle without inserting any additional wait states. To perform a 16-bit memory cycle without wait states, -0WS is derived from an address decode.  

SBHE  

System Byte High Enable is driven low to indicate a transfer of data on the high half of the data bus (D15 to D8).  

The Memory Read bus cycle in ISA bus 

Fig. 13.7(a) The Handshaking Mode of Data Transfer in ISA bus 

The Memory Write bus cycle in ISA bus 

Fig. 13.7(b) The Handshaking Mode of Data Transfer in ISA bus