Design for Testability - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE) PDF Download

Scan Path 

• This approach is also called the Clock Scan Approach. 
• It was invented by Kobayashi et al. in 1968, and reported by Funatsu et al. in 1975, and adopted by NEC. 
• In this approach multiplexing is done by two different clocks instead of a MUX. 
• It uses two-port raceless D-FFs as shown in Figure 39.3. Each FF consists of two latches operating in a master-slave fashion, and has two clocks (C1 and C2) to control the scan input (SI) and the normal data input (DI) separately.
• The two-port raceless D-FF is controlled in the following way:  
• For normal mode operation C2 = 1 to block SI and C1 = 0 →1 to load DI.
• For shift register test mode C1 = 1 to block DI and C2 = 0 →1 to load SI.  

Fig. 39.3 Logic diagram of the two-port raceless D-FF 

• This approach gives a lower hardware overhead (due to dense layout) and less performance penalty (due to the removal of the MUX in front of the FF) compared to the MUX Scan Approach. The real figures however depend on the circuit style and technology selected, and on the physical implementation. 

Level-Sensitive Scan Design (LSSD)  

• This approach was introduced by Eichelberger and T. Williams in 1977 and 1978.  
• It is a latch-based design used at IBM.  
• It guarantees race-free and hazard-free system operation as well as testing.  
• It is insensitive to component timing variations such as rise time, fall time, and delay. It is faster and has a lower hardware complexity than SR modification.
• It uses two latches (one for normal operation and one for scan) and three clocks. Furthermore, to enjoy the luxury of race-free and hazard-free system operation and test, the designer has to follow a set of complicated design rules.
• A logic circuit is level sensitive (LS) iff the steady state response to any allowed input change is independent of the delays within the circuit. Also, the response is independent of the order in which the inputs change 

Fig. 39.4 A polarity-hold latch  

Fig. 39.5 The polarity-hold shift-register latch (SRL) 

LSSD requires that the circuit be LS, so we need LS memory elements as defined above. Figure 39.4 shows an LS polarity-hold latch. The correct change of the latch output (L) is not dependent on the rise/fall time of C, but only on C being `1' for a period of time greater than or equal to data propagation and stabilization time. Figure 39.5 shows the polarity-hold shift-register latch (SRL) used in LSSD as the scan cell. 

The scan cell is controlled in the following way: 

• Normal mode: A=B=0, C=0 → 1.
• SR (test) mode: C=0, AB=10→ 01 to shift SI through L₁ and L₂. 

 Advantages of LSSD  

1. Correct operation independent of AC characteristics is guaranteed.
2. FSM is reduced to combinational logic as far as testing is concerned.
3. Hazards and races are eliminated, which simplifies test generation and fault simulation.  

Drawbacks of LSSD 

1. Complex design rules are imposed on designers. There is no freedom to vary from the overall schemes. It increases the design complexity and hardware costs (4-20% more hardware and 4 extra pins).
2. Asynchronous designs are not allowed in this approach.
3. Sequential routing of latches can introduce irregular structures.
4. Faults changing combinational function to sequential one may cause trouble, e.g., bridging and CMOS stuck-open faults.
5. Test application becomes a slow process, and normal-speed testing of the entire test sequence is impossible. 6. It is not good for memory intensive designs.  

Random Access Scan 

• This approach was developed by Fujitsu and was used by Fujitsu, Amdahl, and TI.
• It uses an address decoder. By using address decoder we can select a particular FF and either set it to any desired value or read out its value. Figure 39.6 shows a random access structure and Figure 39.7 shows the RAM cell [1,6-7]. 

Fig. 39.6 The Random Access structure  

Fig. 39.7 The RAM cell 

• The difference between this approach and the previous ones is that the state vector can now be accessed in a random sequence. Since neighboring patterns can be arranged so that they differ in only a few bits, and only a few response bits need to be observed, the test application time can be reduced.  
• In this approach test length is reduced.
• This approach provides the ability to `watch' a node in normal operation mode, which is impossible with previous scan methods.
• This is suitable for delay and embedded memory testing.
• The major disadvantage of the approach is high hardware overhead due to address decoder, gates added to SFF, address register, extra pins and routing 

Scan-Hold Flip-Flop 

• Special type of scan flip-flop with an additional latch designed for low power testing application.
• It was proposed by DasGupta et al [5]. Figure 39.8 shows a hold latch cascaded with the SFF.  
• The control input HOLD keeps the output steady at previous state of flip-flop.
• For HOLD = 0, the latch holds its state and for HOLD = 1, the hold latch becomes transparent.
• For normal mode operation, TC = HOLD =1 and for scan mode, TC = 1 and Hold = 0.
• Hardware overhead increases by about 30% due to extra hardware the hold latch.  
• This approach reduces power dissipation and isolate asynchronous part during scan.
• It is suitable for delay test [8]. 

Fig. 39.8 Scan-hold flip-flop (SHFF) 

Partial Scan Design 

• In this approach only a subset of flip-flops is scanned. The main objectives of this approach are to minimize the area overhead and scan sequence length. It would be possible to achieve required fault coverage
• In this approach sequential ATPG is used to generate test patterns. Sequential ATPG has number of difficulties such as poor initializability, poor controllability and observability of the state variables etc. Number of gates, number of FFs and sequential depth give little idea regarding testability and presence of cycles makes testing difficult. Therefore sequential circuit must be simplified in such a way so that test generation becomes easier.
• Removal of selected flip-flops from scan improves performance and allows limited scan design rule violations.
• It also allows automation in scan flip-flop selection and test generation
• Figure 39.9 shows a design using partial scan architecture [1].
• Sequential depth is calculated as the maximum number of FFs encountered from PI line to PO line.

Fig. 39.9 Design using partial scan structure 

Things to be followed for a partial scan method  

• A minimum set of flip-flops must be selected, removal of which would eliminate all cycles.
• Break only the long cycles to keep overhead low.
• All cycles other than self-lops should be removed.

Conclusions  

Accessibility to internal nodes in a complex circuitry is becoming a greater problem and thus it is essential that a designer must consider how the IC will be tested and extra structures will be incorporated in the design. Scan design has been the backbone of design for testability in the industry for a long time. Design automation tools are available for scan insertion into a circuit which then generate test patterns. Overhead increases due to the scan insertion in a circuit. In ASIC design 10 to 15 % scan overhead is generally accepted.