Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE) PDF Download

The Programmable Interval Timer 8253

For processors where the timer unit is not internal the programmable interval timer can be used. Fig.14.7 shows the signals for 8253 programmable interval timer. 

Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE)
Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 14.7 The pin configuration of the timer 

Fig.14.8 shows the internal block diagram. There are three separate counter units controlled by configuration register (Fig.14.9).

Each counter has two inputs, clock and gate and one output. The clock is signal that helps in counting by decrementing a preloaded value in the respective counter register. The gate serves as an enable input. If the gate is maintained low the counting is disabled. The timing diagram explains in detail about the various modes of operation of the timer. 

Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 14.8 The internal block diagram of 8253 Table The address map 

Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 14.9 Control Register 

8253 Operating Modes 

Mode 0 Interrupt on terminal count
 Mode 1 Programmable one shot
 Mode 2 Rate Generator
 Mode 3 Square wave rate Generator
 Mode 4 Software triggered strobe
 Mode 5 Hardware triggered strobe 

Mode 0: The output goes high after the terminal count is reached. The counter stops if the Gate is low. (Fig.14.10(a) & (b)). The timer count register is loaded with a count (say 6) when the WR line is made low by the processor. The counter unit starts counting down with each clock pulse. The output goes high when the register value reaches zero. In the mean time if the GATE is made low (Fig.14.10(b)) the count is suspended at the value(3) till the GATE is enabled again. 

Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 14.10(b) Mode 0 count when Gate is low temporarily (disabled) 

Mode 1 Programmable mono-shot 

The output goes low with the Gate pulse for a predetermined period depending on the counter. The counter is disabled if the GATE pulse goes momentarily low. 

The counter register is loaded with a count value as in the previous case (say 5) (Fig.14.11(a)). The output responds to the GATE input and goes low for period that equals the count down period of the register (5 clock pulses in this period). By changing the value of this count the duration of the output pulse can be changed. If the GATE becomes low before the count down is completed then the counter will be suspended at that state as long as GATE is low (Fig.14.11(b)). Thus it works as a mono-shot. 

Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 14.11(b) Mode 1 The Gate pulse is disabled momentarily causing the counter to stop. 

Mode 2 Programmable Rate Generator 

Fig.14.12(a) and (b) shows the waveforms corresponding the Timer operation in this mode. In this mode it operates as a rate generator. The output goes high for a period that equals the time of count down of the count register (3 in this case). The output goes low exactly for one clock period before it becomes high again. This is a periodic operation.

Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 14.12(b) Mode 2 operation when the GATE is disabled momentarily. 

Mode 3 Programmable Square Wave Rate Generator 

It is similar to Mode 2 but the output high and low period is symmetrical. The output goes high after the count is loaded and it remains high for period which equals the count down period of the counter register. The output subsequently goes low for an equal period and hence generates a symmetrical square wave unlike Mode 2. The GATE has no role here. (Fig.14.13). 

Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 14.13 Mode3 Operation: Square Wave generator 

Mode 4 Software Triggered Strobe 

In this mode after the count is loaded by the processor the count down starts. The output goes low for one clock period after the count down is complete. The count down can be suspended by making the GATE low (Fig.14.14(a) (b)). This is also called a software triggered strobe as the count down is initiated by a program. 

Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 14.14(a) Mode 4 Software Triggered Strobe when GATE is high 

Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 14.14(b) Mode 4 Software Triggered Strobe when GATE is momentarily low 

Mode 5 Hardware Triggered Strobe 

The count is loaded by the processor but the count down is initiated by the GATE pulse. The transition from low to high of the GATE pulse enables count down. The output goes low for one clock period after the count down is complete (Fig.14.15). 

Timers - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 14.15 Mode 5 Hardware Triggered Strobe 

Watchdog timer 

A Watchdog Timer is a circuit that automatically invokes a reset unless the system being watched sends regular hold-off signals to the Watchdog.  

Watchdog Circuit 

To make sure that a particular program is executing properly the Watchdog circuit is used. For instance the program may reset a particular flip-flop periodically. And the flip-flop is set by an external circuit. Suppose the flip-flop is not reset for long time it can be known by using external hardware. This will indicate that the program is not executed properly and hence an exception or interrupt can be generated. 

Watch Dog Timer(WDT) provides a unique clock, which is independent of any external clock.  When the WDT is enabled, a counter starts at 00 and increments by 1 until it reaches FF.  When it goes from FF to 00 (which is FF + 1) then the processor will be reset or an exception will be generated.  The only way to stop the WDT from resetting the processor or generating an exception or interrupt is to periodically reset the WDT back to 00 throughout the program.  If the program gets stuck for some reason, then the WDT will not be set.  The WDT will then reset or interrupt the processor. An interrupt service routine will be invoked to take into account the erroneous operation of the program. (getting stuck or going into infinite loop). 

Conclusion 

In this chapter you have learnt about the programmable timer/counter. For most of the embedded processors the timer is internal and exists along with the processor on the same chip. The 8051 microcontroller has 3 different internal timers which can be programmed in various modes by the configuration and mode control register. An external timer chip namely 8253 has also been discussed. It has 8 data lines 2 data lines, 1 chip select line and one read and one write control line. The 16 bit counts of the corresponding registers can be loaded with two consecutive write operations. Counters and Timers are used for triggering, trapping and managing various real time events. The least count of the timer depend on the clock. The stability of the clock decides the accuracy of the timings.  Timers can be used to generate specific baud rate clocks for asynchronous serial communications. It can be used to measure speed, frequency and analog voltages after Voltage to Frequency conversion. One important application of timer is to generate Pulse-Width-Modulated (PWM) waveforms. In 8253 the GATE and pulse together can be used together to generate pulse with different widths. These modulated pulses are used in electronic power control to reduce harmonics and hence distortions. 

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