Interrupts - 1 | Embedded Systems (Web) - Computer Science Engineering (CSE) PDF Download

Introduction 

Real Time Embedded System design requires that I/O devices receive servicing in an efficient manner so that large amounts of the total system tasks can be assumed by the processor with little or no effect on throughput. The most common method of servicing such devices is the polled approach. This is where the processor must test each device in sequence and in effect “ask” each one if it needs servicing. It is easy to see that a large portion of the main program is looping through this continuous polling cycle and that such a method would have a serious, detrimental effect on system throughput, thus, limiting the tasks that could be assumed by the microcomputer and reducing the cost effectiveness of using such devices. A more desirable method would be one that would allow the microprocessor to be executing its main program and only stop to service peripheral devices when it is told to do so by the device itself. In effect, the method would provide an external asynchronous input that would inform the processor that it should complete whatever instruction that is currently being executed and fetch a new routine that will service the requesting device. Once this servicing is complete, however, the processor would resume exactly where it left off. This can be effectively handled by interrupts.  

A signal informing a program or a device connected to the processor that an event has occurred. When a processor receives an interrupt signal, it takes a specified action depending on the priority and importance of the entity generating the signal. Interrupt signals can cause a program to suspend itself temporarily to service the interrupt by branching into another program called Interrupt Service Subroutines (ISS) for the specified device which has caused the interrupt.  

Types of Interrupts 

Interrupts can be broadly classified as  
 -  Hardware Interrupts  
 These are interrupts caused by the connected devices.  
 - So ftware Int errupts  
 These are interrupts deliberately introduced by software instructions to generate user defined exceptions  
 - Trap
 These are interrupts used by the processor alone to detect any exception such as divide by zero  
 Depending on the service the interrupts also can be classified as
 -  Fixed interrupt

  • Address of the ISR built into microprocessor, cannot be changed 
  • Either ISR stored at address or a jump to actual ISR stored if not enough bytes available 

 - Ve ctored int errupt 

  • Peripheral must provide the address of the ISR 
  • Common when microprocessor has multiple peripherals connected by a system bus 

• Compromise between fixed and vectored interrupts 
 – One interrupt pin 
 – Table in memory holding ISR addresses (maybe 256 words)
 – Peripheral doesn’t provide ISR address, but rather index into table 

  • Fewer bits are sent by the peripheral 
  • Can move ISR location without changing peripheral 

Maskable vs. Non-maskable interrupts 
 – Maskable: programmer can set bit that causes processor to ignore interrupt 

  • This is important when the processor is executing a time-critical code 

– Non-maskable: a separate interrupt pin that can’t be masked 

  • Typically reserved for drastic situations, like power failure requiring immediate backup of data to non-volatile memory 

Example: Interrupt Driven Data Transfer (Fixed Interrupt) 

Fig.15.1(a) shows the block diagram of a system where it is required to read data from a input port P1, modify (according to some given algorithm) and send to port P2. The input port generates data at a very slow pace. There are two ways to transfer data 

(a) The processor waits till the input is ready with the data and performs a read operation from P1 followed by a write operation to P2. This is called Programmed Data Transfer (b) The other option is when the input/output device is slow then the device whenever is ready interrupts the microprocessor through an Int pin as shown in Fig.15.1. The processor which may be otherwise busy in executing another program (main program here) after receiving the interrupts calls an Interrupt Service Subroutine (ISR) to accomplish the required data transfer. This is known as Interrupt Driven Data Transfer. 

Interrupts - 1 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig: 15.1(a) The Interrupt Driven Data Transfer

PC-Program counter, P1-Port 1 P2-Port 2, μC-Microcontrolle

Interrupts - 1 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 15.1(b) Flow chart for Interrupt Service 

Fig.15.1(b) describes the sequence of action taking place after the Port P1 is ready with the data. Example: Interrupt Driven Data Transfer (Vectored Interrupt) 

Interrupts - 1 | Embedded Systems (Web) - Computer Science Engineering (CSE)
Interrupts - 1 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 15.2(b) Vectored Interrupt Service 

Interrupts in a Typical Microcontroller (say 8051) 

Interrupts - 1 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 15.3 The 8051 Architecture 

The 8051 has 5 interrupt sources: 2 external interrupts, 2 timer interrupts, and the serial port interrupt. 

These interrupts occur because of 
 1. timers overflowing
 2. receiving character via the serial port
 3. transmitting character via the serial port
 4. Two “external events” 

Interrupt Enables 

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in a Special Function Register (SFR) named IE (Interrupt Enable). This register also contains a global disable bit, which can be cleared to disable all interrupts at once.  

Interrupt Priorities 

Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in the SFR named IP (Interrupt Priority). A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. In operation, all the interrupt flags are latched into the interrupt control system during State 5 of every machine cycle. The samples are polled during the following machine cycle. If the flag for an enabled interrupt is found to be set (1), the interrupt system generates a CALL to the appropriate location in Program Memory, unless some other condition blocks the interrupt. Several conditions can block an interrupt, among them that an interrupt of equal or higher priority level is already in progress. The hardware-generated CALL causes the contents of the Program Counter to be pushed into the stack, and reloads the PC with the beginning address of the service routine. 

Interrupts - 1 | Embedded Systems (Web) - Computer Science Engineering (CSE)Interrupts - 1 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Interrupts - 1 | Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 15.4 8051 Interrupt Control System 

Interrupts - 1 | Embedded Systems (Web) - Computer Science Engineering (CSE)
TF0: Timer 0 Interrupt
 TF1: Timer 1 Interrupt
 RI,TI: Serial Port Receive/Transmit Interrupt 

The service routine for each interrupt begins at a fixed location (fixed address interrupts). Only the Program Counter (PC) is automatically pushed onto the stack, not the Processor Status Word (which includes the contents of the accumulator and flag register) or any other register. Having only the PC automatically saved allows the programmer to decide how much time should be spent saving other registers. This enhances the interrupt response time, albeit at the expense of increasing the programmer’s burden of responsibility. As a result, many interrupt functions that are typical in control applications toggling a port pin for example, or reloading a timer, or unloading a serial buffer can often be completed in less time than it takes other architectures to complete. 

Interrupt Number  Interrupt  Vector Address Description  
00003hEXTE RNAL 0
1000BhTIMER /COUNTER 0
20013hEXTE RNAL 1
3001BhTIMER /COUNTER 1
40023hERIAL PORT  


Simultaneously occurring interrupts are serviced in the following order: 

1. External 0 Interrupt
 2. Timer 0 Interrupt
 3. External 1 Interrupt
 4. Timer 1 Interrupt
 5. Serial Interrupt 

The document Interrupts - 1 | Embedded Systems (Web) - Computer Science Engineering (CSE) is a part of the Computer Science Engineering (CSE) Course Embedded Systems (Web).
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