Bipolar Junction Transistors | Solid State Physics, Devices & Electronics PDF Download

Bipolar Junction Transistors 

Transistor Construction 

Transistor is a three-layer semiconductor device consisting of either two n- and one p-type layer of material or two p- and one n-type layers of material. The former is called npn transistor, while latter is called an pnp transistor. Both are shown in figure with proper biasing.

Figure: Types of transistors: (a) pnp (b) npn.

The emitter layer is heavily doped, the base lightly doped, and the collector only lightly doped. The outer layers have widths much greater than the sandwiched p- or n-type material. The ratio of the total width to that of the center layer is 150:1. The doping of the sandwiched layer is also considerably less than that of the outer layer (typically, 10:1 or less).This lower doping level decreases the conductivity (increases the resistance) of this material by limiting the number of “free” carriers.  
The terminals have been indicated by the capital letters E for emitter, C for collector, and B for base. The term bipolar junction transistor (BJT) reflects the fact that holes and electrons participate in the injection process into the oppositely polarized material.

Transistor Operation 

The basic operation of the transistor is described using pnp transistor as shown in       figure (a). The operation of the npn transistor is exactly the same if the roles played by the electron and holes are interchanged. In figure the pnp transistor has been redrawn without the base-to-collector bias (similar to forward-biased diode). The depletion region has been reduced in width due to applied bias, resulting in a heavy flow of majority carriers from p- to the n-type material.  

Figure : Forward-biased junction of a pnp transistor.

Let us now remove the base-to-emitter bias of the pnp transistor of figure (a) as shown in figure (similar to reverse-biased diode). Recall that the flow of majority carriers is zero, resulting in only a minority-carrier flow. Thus  
“One p-n junction of a transistor is reversed biased, while the other is forward biased.”  

Figure : Reverse based junction of a pnp transistor.  

In figure both biasing potentials have been applied to a pnp transistor, with the resulting majority and minority-carrier flow indicated. The widths of the depletion regions, indicating clearly which junction is forward-biased and which is reversed-biased. A large number of majority carriers will diffuse across the forward-biased p-n junction into the n-type material. Since n-type material is very thin and has low conductivity, a very small number of these carriers will take this path of high resistance to the base terminal. The larger number of these majority carriers will diffuse across the reverse biased junction into the p-type material connected to the collector terminal. Thus there has been an injection of minority carriers into the n-type base region material.  Combining this with the fact that all the minority carriers in the depletion region will cross the reversed-biased junction of a diode accounts for the flow indicated in the figure.

 Figure : Majorit and minority carrier flow of a pnp transistor.

Applying Kirchhoff’s current law to the transistor of figure as if it were a single node, we obtain  I_E = I_C + I_B
The minority current component is called the leakage current and is given by the symbol  I_CO (collector current with emitter terminal open). The collector current, therefore is:  

Transistor Configurations 

➤ Common-Base Configuration 

The common-base configuration with pnp and npn transistors are shown in figure. The common-base terminology is derived from the fact that the base is common to both the input and output sides of the configurations.

Figure : Notation and symbols used with the common base-configuration: (a) pnp transistor; (b) npn transistor.
To fully describe the behavior of a three terminal device such as common base amplifiers requires two set of characteristics- one for the driving point or input parameters and the other for the output side. 

• Input Characteristics
  The input set for the common base amplifiers as shown in figure will relate an input current (I_E) to an input voltage (V_BE) for various levels of output voltage (V_CB).
  Figure : Input or driving point characteristics for a common-base silicon transistor. 
• Output Characteristics
  The output set will relate an output current (I_C) to an output voltage (V_CB) for various levels of input current (I_E). The output characteristics have three basic regions of interest: the active, cutoff, and saturation regions. The active region is the region normally employed for linear (undistorted) amplifiers.
  In the active region the collector-base junction is reversed-biased, while the base-emitter junction is forward biased.
  Figure : Output or collector characteristics for a common-base transistor amplifier. The circuit condition that exists when I_E = 0 for common base configuration is shown in figure. Note that I_CBO is temperature dependent and increases so rapidly with temperature.  
  In the output characteristics as the emitter current increases above zero, the collector current increases to a magnitude essentially equal to that of the emitter current as determined by the basic transistor current relations. Note also the almost negligible effect of V_CB on the collector current for the active region. In the cutoff region the collector-base and base-emitter junctions are both reversed biased.
  In the saturation region the collector-base and base-emitter junctions are both forward biased.
• Alpha (α)  
  In the dc mode the levels of I_C and I_E due to majority carriers are related by a quantity called alpha and defined by the following equations:
  α_dc = I_C/I_E where I_C and I_E are the levels of current at the point of operation.
  Thus
  For ac situations where the point of operation moves on the characteristics curve, an ac alpha is defined by
  The ac alpha is formally called the common-base, short-circuit, amplification factor.
  The typical values of voltage amplification (V₀/V_i)for the common-base configuration vary from 50 to 300. The current amplification (I_C/I_E) is always less than 1 for the common-base configuration.

➤ Common Emitter Configuration  
The common-emitter configuration with pnp and npn transistors are shown in figure. The common-emitter terminology is derived from the fact that the emitter is common to both the input and output sides of the configurations.

Figure : Notation and symbols used with the common-emitter configuration. 

To fully describe the behavior of a three terminal device such as common emitter amplifier requires two set of characteristics- one for the input or base-emitter circuit and one for the output or collector-emitter circuit.
The output characteristics will relate an output current (I_C) to an output voltage (V_CE) for various levels of input current (I_B). The input characteristics for the common emitter amplifiers will relate an input current (I_B) to an input voltage (V_BE) for various levels of output voltage (V_CE).
In the active region the collector-base junction is reversed-biased, while the base-emitter junction is forward biased.
In the cutoff region the collector-base and base-emitter junctions are both reversed biased.
In the saturation region the collector-base and base-emitter junctions are both forward biased.

Figure : Characteristics of a silicon transistor in the common emitter configuration: (a) Collector characteristics; (b) base characteristics.
Since  
or

Figure : Circuit condition related to I_CEO.

• Beta (β)
  In the dc mode the levels of I_C and I_B are related by a quantity called beta and defined by the following equations: β_dc = I_C/I_B where I_C and I_B are the levels of current at the point of operation. For ac situations where the point of operation moves on the characteristics curve, an ac beta is defined by  The formal name for β_ac is common emitter forward-current amplification factor.

➤ Common-Collector Configuration  
The third and final transistor configuration is the common–collector configuration, shown in figure with the proper current directions and voltage notation. The common collector configuration is used primarily for impedance-matching purposes since it has a high input impedance and low output impedance, opposite to that of the common-base and common-emitter configurations.

A common collector circuit configuration is provided in figure with the load resistor connected from emitter to ground. Note that the collector is tied to ground even though the transistor is connected in a manner similar to the common emitter configuration. For all practical purposes, the output characteristics of the CC configuration are same as for the CE configuration.

DC Biasing-BJTs 

➤ Introduction 
The analysis or design of a transistor amplifier requires knowledge of both the dc and ac response of the system. The improved output ac power level is the result of a transfer of energy from the applied dc supplies. The analysis or design of any electronic amplifier, therefore, has two components: the dc portion and the ac portion. Fortunately, the superposition theorem is applicable and the investigation of the dc conditions can be totally separated from the ac response. However, one must keep in mind that during the design stage the choice of parameters for the required dc levels will affect the ac response and vice-versa.  
The dc level of operation of a transistor is controlled by a number of factors, including the range of possible operating points on the device characteristics. Each design will also determine the stability of the system, that is, how sensitive the system is to temperature variations.  
Although a number of networks will be analyzed, there is an underlying similarly between the analysis of each configuration due to the recurring use of the following important basic relationships for a transistor:  
V_BE = 0.7V, I_E = (β+1)I_B≌I_C and I_C = βI_B
➤ Operating Point
Since the operating point is a fixed point on the characteristics it is also called the quiescent point (abbreviated Q-point). By definition, quiescent means quiet, still, inactive. Figure shows a general output device characteristic with four operating points indicated. The biasing circuit can be designed to set the device operation at any of these points or others within the active region. The maximum ratings are indicated on the characteristics by a horizontal line for the maximum collector current  and a vertical  line at the maximum collector-to-emitter voltage . The maximum power constraint  is defined by the curve  in the same figure. At the lower end of the scales are the cutoff regions, defined by I_B ≤ 0 μA and the saturation region, defined by V_CE ≤.

Figure : Various operating points within the limits of operation of a transistor.

If no bias were used, the device would initially be completely off, resulting in a Q-point at A-namely zero current through the device (and zero voltage across it). Since it is necessary to bias a device so that it can respond to the entire range of an input signal point A would not be suitable. For point B if a signal is applied to the circuit, the device will vary in current and voltage from operating point, allowing the device to react to both the positive and negative excursion of the input signal. If the input signal is properly chosen, the voltage and current of the device will vary but not enough to drive the device into cutoff or saturation. Point C would allow some positive and negative variation of the output signal but the peak-to-peak value would be limited by the proximity of V_CE = 0V , I_C = 0 mA . Operating at point C also raise some concern about the nonlinearities introduced by the fact that the spacing between I_B curves is rapidly changing in this region.  
In general, it is preferable to operate where the gain of the device is fairly constant (or linear) to ensure that the amplification over the entire swing of input signal is the same. Point D sets the device operating point near the maximum voltage and power level. The output voltage swing in the positive direction is thus limited if the maximum voltage is not to be exceeded. Point B is a region of more linear spacing and therefore, seems the best operating point in terms of linear gain and largest possible voltage and current swing. This is usually the desired condition for small-signal amplifiers but not the case necessarily for power amplifiers. In this discussion, we will be concentrating primarily on biasing the transistor for small-signal amplification operation.  
Having selected and biased the BJT at a desired operating point, the effect of temperature must also be taken into account. Temperature causes the device parameters such as the transistor current gain (β_ac) and the transistor leakage current (I_CEO) to change. Higher temperatures result in increased leakage currents in the device, thereby changing the operating condition set by the biasing network. The result is that the network design must also provide a degree of temperature stability so that temperature changes result in minimum changes in the operating point. This maintenance of the operating point can be specified by a stability factor, S, which indicates the degree of change in operating point due to a temperature variation. A highly stable circuit is desirable and the stability of a few basic bias circuits will be compared.  
For the BJT to be biased in its linear or active operating region the following must be true: 

• The base-emitter junction must be forward-biased (p-region voltage more positive) with a resulting forward-bias voltage of about 0.6 to 0.7 V. 
• The base-collector junction must be reverse-biased (n-region more positive), with the reverse-bias voltage being any value within the maximum limits of the device.  

Operation in the cutoff, saturation and linear regions of the BJT characteristic are provided as follows: 

1. Linear-region operation:  
   Base-emitter junction forward biased
   Base-collector junction reversed biased
2. Cutoff-region operation:  
   Base-emitter junction reverse biased
   Base-collector junction reversed biased 
3. Saturation-region operation:
   Base-emitter junction forward biased
   Base-collector junction forward biased 

Fixed-Bias Circuit   

The fixed-bias circuit of figure provides a relatively straightforward and simple introduction to transistor dc bias analysis. Even though the network employs an npn transistor, the equations and calculations apply equally well to a pnp transistor configuration merely by changing all current directions and the voltage polarities.  

Figure : Fixed-bias circuit
For the dc analysis the network can be isolated from the indicated ac levels by replacing the capacitors with an open circuit equivalent. In addition, the dc supply V_CC can be separated into two supplies (for analysis purposes only) as shown in figure to permit a separation of input and output circuits. It also reduces the linkage between the two to the base current I_B. 

➤ Q-Point

• Forward Bias of Base-Emitter
  Consider first the base-emitter circuit loop of figure shown. Writing Kirchhoff’s voltage equation in the clockwise direction for the loop, we obtain -V_CC+I_BR_B+V_BE = 0
  Note the polarity of the voltage drop across RB as established by the indicated direction of I_B. Solving the equation for the current IB will result in the following:

Since the supply voltage V_CC and the base-emitter voltage V_BE are constants, the selection of a base resistor, R_B sets the level of base current for the operating point.

• Collector-Emitter Loop  
  The collector-emitter section of the network appears in figure with the indicated direction of current I_C and the resulting polarity across R_C .

The magnitude of the collector current is related directly to I_B through  
I_C = βI_B
It is interesting to note that since the base current is controlled by the level of R_B and I_C is related to I_B by a constant β the magnitude of I_C is not a function of the resistance R_C . Change R_C to any level and it will not affect the level of I_B or I_C as long as we remain in the active region of the device. However, as we shall see, the level of R_C will determine the magnitude of V_CE, which is an important parameter.  
Applying Kirchhoff’s voltage law in the clockwise direction around the indicated closed loop of figure will result in the following:
−V_CC+I_CR_C + V_CE = 0 ⇒ V_CE=V_CC − I_CR_C 
As a brief review of single and double subscript notation recall that  V_CE =V_C-V_E

Figure : Measuring V_CE and V_C .
where V_CE is the voltage from collector to emitter and V_C and V_E are the voltages from collector and emitter to ground respectively. But in this case since V_E=0V, we have V_CE=V_C.
In addition, since V_BE =V_B− V_E  and V_E = 0V then V_BE =V_B.
Keep in mind that voltage levels such as V_CE are determined by placing the positive lead of the voltmeter at the collector terminal with the negative lead at the emitter terminal as shown in figure. V_C is the voltage from collector to ground and is measured as shown in the same figure. In this case the two readings are identical, but in the networks to follow the two can be quite different.  

➤ Transistor Saturation  
The term saturation is applied to any system where levels have reached their maximum values. For a transistor operating in the saturation region the current is a maximum value for the particular design. Change the design and the corresponding saturation level may rise or drop.  
Saturation conditions are normally avoided because the base-collector junction is no longer reverse-biased and the output amplified signal will be distorted. An operating point in the saturation region is depicted in figure. Note that it is in a region where the characteristic curves join and the collector-to-emitter voltage is at or below. In 

addition, the collector current is relatively high on the characteristics.
If we approximate the curves of figure (a) by those appearing in figure (b), a quick direct method for determining the saturation level becomes apparent. In figure (b) the current is relatively high and the voltage VCE is assumed to be zero volts. Applying Ohm’s law the resistance between collector and emitter terminals can be determined as follows: 

For saturation current set V_CE = 0V and find . For the fixed-bias configuration of figure the short circuit has been applied, causing the voltage across R_C to be the applied voltage V_CC. The resulting saturation current for the fixed-bias configuration is  

➤ Load-Line Analysis  
We will now investigate how the network parameters define the possible range of  Q-points and how the actual Q-point is determined.

Figure : Load-line analysis (a) the network (b) the device characteristics.

The network of figure (a) establishes an output equation that relates the variables I_C and V_CE in the following manner: V_CE =V_CC− I_C R_C 
The output characteristics of the transistor also relate the same two variables I_C and V_CE in figure (b).

Figure : Fixed-bias load.

We must now superimpose the straight line defined by equation V_CE =V_CC− I_C R_C on the characteristics. If we choose I_C to be 0 mA , we are specifying the horizontal axis as the line on which one point is located. By substituting I_C = 0 mA , we find that  defining one point for the straight line as shown in figure.
If we now choose V_CE to be 0 V , which establishes the vertical axis as the line on which the second point will be defined, we find that I_C is determined by the following equation:
 
By joining the two points defined by equation  

the  straight line established by equation V_CE =V_CC − I_CR_C can be drawn. The resulting line on the graph of figure is called the load line since it is defined by the load resistor R_C. By solving for the resulting level of I_B the actual Q-point can be established. If the level of I_B is changed by varying the value of R_B the Q-point moves up or down the load line as shown in figure.  

Figure : Movement of Q-point with increasing levels of I_B.

NOTE: For Fixed R_B if temperature of the device increases the Q-point will moves towards the saturation region as shown in figure. Since I_C = βI_B+I_CEO with increase in temperature reverse current I_CEO = (β+) I_CBO increases.  

If V_CC is held fixed and R_C changed, the load line will shift as shown in figure. If I_B is held fixed, the Q-point will move as shown in the same figure. 

Figure : Effect of increasing levels of R_C on the load line and Q-point.

If R_C is fixed and V_CC varied, the load line shifts as shown in figure. 

 Figure : Effect of lower values of V_CC on the load line and Q-point.

Example: Determine the following for the fixed-bias configuration of figure shown below.

(a)

(b)
(c) V_B and V_C
(d) V_BC
(e) Saturation level.

(d) Using double-subscript notation yields  
V_BC = V_B - V_C = 0.7V - 6.83V = -6.13V
With the negative sign revealing that the junction is reversed-biased, as it should be for linear amplification.  
(e)
 which is far from the saturation level and about one-half the maximum value for the design.

Emitter-Stabilized Bias Circuit 

The dc bias network of figure contains an emitter resistor to improve the stability level over that of the fixed-bias configuration.  

Figure : BJT circuit with emitter resistor.

➤ Q-Point  
The analysis will be performed by first examining the base-emitter loop and then using the results to investigate the collector-emitter loop.

• Base–Emitter Loop
  The base-emitter loop of the network can be redrawn as shown in figure. Writing Kirchhoff’s voltage law around the indicated loop in the clockwise direction will result in the following equation:    
  -V_CC+I_BR_B+V_BE+I_ER_E= 0
  V_CC − I_BR_B− V_BE − (β + 1) I_BR_E = 0 ∵ I_E = (β+ 1)I_B
  Grouping terms will then provide the following:
   
  Note that the only difference between this equation for IB and that obtained for the fixed-bias configuration is the term (β + 1) R_E.  
  There is an interesting result that can be derived from equation  if the equation is used to sketch a series network that would result in the same equation. Such is the case for the network of figure. Solving for the current I_B will result in the same equation obtained above. Note that aside from the base-to-emitter voltage V_BE the resistor R_E is reflected back to the input base circuit by a factor (β + 1). In other words, the emitter resistor, which is part of the collector–emitter loop, “appears as” (β + 1) R_E in the base-emitter loop. Since β is typically 50 or more, the emitter resistor appears to be a great deal larger in the base circuit.
  In general, therefore, for the configuration of figure,  R_i = (β+1)R_E
  This equation is one that will prove useful in the analysis to follow. In fact, it provides a fairly easy way to remember equation  Using Ohm’s law, we know that the current through a system is the voltage divided by the resistance of the circuit. For the base-emitter circuit the net voltage is V_CC −V_BE. The resistance levels are R_B plus R_E reflected by (β + 1) .  
• Collector–Emitter Loop
  The collector-emitter loop is redrawn in figure.  Writing Kirchhoff’s voltage law for the indicated loop in the clockwise direction will result in I_ER_E + V_CE + I_CR_C - V_CC = 0
  Substituting I_C ≈ I_E and grouping terms gives
  Figure : Collector-emitter loop.
  V_CE =V_CC− I_C ( R_C + R_E)
  The single-subscript voltage V_E is the voltage from emitter to ground and is determined by  V_E =I_ER_E
  while the voltage from collector to ground can be determined from V_CE =V_C− V_E or  V_C =V_CE+ V_E and  V_C =V_CC − I_CR_C
  The voltage at the base with respect to ground can be determined from  V_B =V_CC− I_B R_B or V_B =V_BE + V_E
•  Saturation Level  
  The collector saturation level or maximum collector current for an emitter-bias design can be determined using the same approach applied to the fixed-bias configuration:  
  
  Figure : Determining  for the emitter-stabilized bias circuit.  
  The addition of the emitter resistor reduces the collector saturation level below that obtained with a fixed-bias configuration using the same collector resistor. 
• Load-Line Analysis  
  The load-line analysis of the emitter-bias network is only slightly different from that encountered for the fixed-bias configuration. The level of I_B as determined by equation   defines the level of I_B on the characteristics of figure (denoted ).
  The collector-emitter loop equation that defines the load line is the following:  
  
  as obtained for the fixed-bias configuration. Choosing V_CE = 0V gives  
  as shown in figure. Different levels of will, of course, move the Q-point up or  down the load line.  

Example: For the emitter bias network of figure shown below, determine: 

(a) I_B
(b) I_C
(c) V_CE
(d) V_C
(e) V_E
(f) V_B
(g) V_BC
(h)

which is about twice the level of .  

Voltage-Divider Bias 

In the previous bias configurations the bias current  and voltage  were a function of the current gain (β) of the transistor. However, since β is temperature sensitive, specially for silicon transistors, and the actual value of beta is usually not well defined, it would be desirable to develop a bias circuit that is less dependent, or in fact,  independent of the transistor beta. The voltage-divider bias configuration of figure is such a network. If analyzed   on an exact basis the sensitivity to changes in beta is quite small.

➤ Q-point  
The input side of the network can be redrawn as shown in figure for the dc analysis. The Thevenin equivalent network for the network to the left of the base terminal can then be found in the following manner.  

• Thevenin’s Resistance (R_Th) :  The voltage source is replaced by a short-circuit equivalent as shown in figure .
   
  
• Thevenin’s Voltage ( E_Th) :  The voltage source V_CC is returned to the network and the open-circuit Thevenin voltage of figure determined as follows:
  Applying the voltage-divider rule:  

The Thevenin network is then redrawn as shown in figure 3.39 and  can be determined by first applying Kirchhoff’s voltage law in the clockwise direction for the loop indicated: -E_Th + I_BR_Th + V_BE  + I_ER_E = 0

Once I_B is known the remaining quantities of the network can be found in the same manner as developed for the emitter-bias configuration. That is V_CE = V_CC-I_C(R_C+R_E).
The remaining equations for V_E , V_C and V_B are also the same as obtained for the emitter-bias configuration.  

➤ Transistor Saturation  
The output collector-emitter circuit for the voltage-divider configuration has the same appearance as the emitter-biased circuit. The resulting equation for the saturation current (when V_CE is set to zero volts on the schematic) is therefore the same as obtained for the emitter-biased configuration. That is,

➤ Load-Line Analysis  
The similarities with the output circuit of the emitter-biased configuration result in the same intersections for the load line of the voltage-divider configuration. The load line will therefore have the same appearance as that of figure, with  
 and  
The level of I_B is of course determined by a different equation for the voltage-divider bias and the emitter-bias configurations.  

Example: Determine the dc bias voltage V_CE and the current I_C for the voltage-divider configuration of figure shown below.  

⇒ V_CE= 22 − ( 0.85mA) (10k Ω + 1.5k Ω ) = 12.22 V

DC Bias with Voltage Feedback  

An improved level of stability can also be obtained by introducing a feedback path from collector to base as shown in figure. 

➤ Q-point (Base-Emitter Loop)
Figure shows the base-emitter loop for the voltage feedback configuration.  Writing Kirchhoff’s voltage law around the indicated loop in the clockwise direction will result in  
−V_CC+I_C′ R_C + I_BR_B + V_BE + I_ER_E = 0

It is important to note that the current through R_C is not I_C but I_C′ (where I_C′ = I_C+I_B ≈ I_C). Thus
 
In general, therefore, the feedback path results in a reflection of the resistance R_C back to the input circuit, much like the reflection of R_E.  
In general, the equation for I_B had the following format:  with the absence of R′ for the fixed-bias configuration, R′ = R_E for the emitter-bias setup (with (β + 1)≅ β ), and R′ = R_C+R_E for the collector-feedback arrangement. The voltage V ′ is the difference between two voltage levels.
 ∵ I_C = βI_B

➤ Collector-Emitter Loop

The collector-emitter loop for the network is provided in figure. Applying Kirchhoff’s voltage law around the indicated loop in the clockwise direction will result in  −V_CC+I_C′ R_C + V_CE + I_ER_E = 0

−V_CC+I_C (R_C + R_E) + V_CE = 0
∵ I'_C = I_C and I_E = I_C
⇒ V_CE = V_CC − I_C ( R_C + R_E)
which is exactly as obtained for the emitter-bias and voltage-divider bias configurations.

➤ Saturation Conditions  

Using the approximation I_C′ = I_C the equation for the saturation current is the same as obtained for the voltage-divider and emitter-bias configurations. That is,
 

➤ Load-Line Analysis  
Continuing with the approximation I_C′ = I_C will result in the same load line defined for the voltage-divider and emitter-biased configurations. The level of  will be defined by 

the chosen bias configuration.  

Example: Determine the quiescent levels of and for the network of figure shown below.  

I_B = 11.91 μA