The Central processing unit of the system can be divided into two sections: a Data section and a Control section.
The ALU, the registers, and the interconnecting buses are collectively referred to as datapath. Every bit in datapath is functionally identical. The datapath is competent enough of executing certain operations on data items.
Control Section
The control section is basically referred to as the control unit, whose main goal is to send control signals to the datapath.
Bus: A Bus is defined as a collection of wires or distinct lines which are meant to carry address, data, and control information.
Data Bus: Used for transmission of data. The number of data lines conforms to the number of bits in a word.
Address Bus: It contains the address of the data in the main memory location from where it can be accessed.
Control Bus: It carries control signals like it is used to tell the direction of data transfer and to coordinate the timing of events during the data transfer.
PC (Program Counter): Holds the address of the next instruction
IR (Instruction Register): Holds the executing instruction
Instruction Cache: ‘Fast’ memory where the next instruction comes from Reg[index]
(Register File): It has 32 registers
Arithmetic Logic Unit (ALU): This part is responsible for performing all arithmetic and logical operations.
Data Cache: Data read from or written to ‘fast’ memory
Multiplexer: Multiple inputs selects one output based upon control signal(s)
Single-Cycle Data Path: Each instruction executes in one clock cycle
Multi-Cycle Data Path: Each instruction takes multiple clock cycles
Single-Cycle Data Path
Multi-Cycle Data Path
It is further classified into three types on the basis of ALU Data Paths.
Bus Configurations in the CPU:
Memory
Separate memory
Single memory
Memory Interfacing
This concept is used to integrate the CPU and memory unit. Pins are mapped between the CPU and main memory to get the required functioning.
The latch is used so that single pins can be used for carrying data as well as address i.e, the same lines are used to carry data and address.
Memory Accessing Schemes
One-Bus Organization
Two-Bus Organization
Three-Bus Organization
Instruction Cycle
The instruction cycle can be divided into three phases:
The basic actions during fetching an instruction, executing an instruction, or handling an interrupt are defined by a sequence of micro-operations.
Effective Address Calculation
Condition Codes/ Program Status Word: The processor keeps track of some information about the results of various operations for use by subsequent conditional branch instructions, by recording the necessary data into individual bits known as condition code flags.
It is further divided into two parts:
Conditional Flags: Important flags of status/condition code register:
Control Flags: Important control flags are:
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