ALU & Data Path - Computer Architecture & Organisation (CAO) - Computer

Table of Contents
1. Introduction
2. CPU Registers and Their Roles
3. Data Path, BUS and Control
4. One-Bus Organisation
5. Two-Bus Organisation
6. Three-Bus Organisation
7. Comparative Advantages of Multiple-Bus Organisations
8. Practical Notes and Design Trade-offs
9. Summary
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Introduction

Representing and storing numbers was the basic operation of early computers. The next major advance was performing arithmetic and logical computations on those numbers. These operations are performed by the computer's arithmetic logic unit (ALU), which is the mathematical brain of a computer. One of the first widely used ALU implementations was the Intel 74181, a 7400-series TTL integrated circuit released in 1970.

The ALU is a digital circuit that provides arithmetic (for example, addition, subtraction, increment, decrement) and logic operations (for example, AND, OR, NOT, XOR). It is the fundamental building block of the central processing unit (CPU). A modern CPU contains one or more ALUs, a control unit, and a set of registers. The control unit issues signals that tell the ALU which operation to perform and coordinates data movement. Registers are small, very fast storage elements available to the CPU; the ALU reads operands from registers and writes results back to registers.

Central Processing

CPU Registers and Their Roles

• Program Counter (PC): A CPU register that holds the address of the next instruction to be fetched from memory. After each instruction fetch, the PC is updated so the CPU knows where to fetch the next instruction. It acts as a digital counter used to track program progress.
• Instruction Register (IR): Holds the current instruction fetched from memory. The IR presents the instruction bits to the instruction decoder so the control unit can generate appropriate control signals.
• Memory Address Register (MAR): Temporarily holds the memory address for a read or write operation. When the CPU needs to fetch data or store data in memory, the address is placed in the MAR.
• Memory Data Register (MDR) / Memory Buffer Register (MBR): Temporarily holds the data read from memory or the data to be written into memory. The MDR provides the actual data transfer between CPU and memory.
• General-Purpose Registers (GPRs): Used to hold operands and intermediate results. GPRs are accessible by instructions and by the ALU and are typically used for arithmetic, logic, and address calculations.

Data Path, BUS and Control

The CPU can be conceptually divided into two main sections: the data path and the control section. The data path contains registers, the ALU, and the interconnecting buses that move data between components. The control section generates the timing and control signals to orchestrate the operations of the data path.

BUS: A bus is a communication system that transfers data between components inside a computer, or between computers. It consists of physical media such as wires or traces and associated control signals and protocols. Historically, a bus was a set of parallel electrical wires; modern systems may use multiplexed wires or serial links, but the conceptual role is the same. The registers, ALU, and interconnecting bus(s) together form the data path.

Types of Bus

• Address bus: Carries memory addresses used to access memory locations.
• Data bus: Carries actual data values between components.
• Control bus: Carries control and timing signals (for example, read/write, interrupt, clock).
• Power/clock bus: Carries power rails and clock signals used across the system.

A bus may be dedicated to a single purpose or multiplexed to serve multiple roles. Different bus organisations lead to different designs of the data path.

One-Bus Organisation

In a one-bus organisation, a single common bus connects the set of general-purpose registers, the PC, the IR, the MAR, the MDR, and the ALU. Any transfer among registers or between a register and memory uses this one bus. Because there is only one bus, at any given time only one transfer can occur on the bus.

Consequences and characteristics:

• Only one operand can be read from the bus at a time; if an operation needs two operands, the read must be performed sequentially.
• This sequential access increases the number of cycles needed for multi-operand instructions and slows down execution compared with multi-bus designs.
• The main advantage is simplicity and low hardware cost; the main disadvantage is limited parallelism and throughput.

One Bus Organisation

Two-Bus Organisation

To reduce the sequential bottleneck of the single bus, designers introduced the two-bus organisation. In this architecture there are two separate buses so more than one transfer can be performed concurrently. Typical usage is one bus for reading operands and the other for writing results or for simultaneous reads.

Key points:

• Two operands can be fetched simultaneously from two different registers using the two buses, allowing the ALU to operate without waiting for two sequential reads.
• When both buses are busy, results may be held in a temporary register (a local buffer) until a bus becomes free, then written back to the destination register.
• There are variants such as an in-bus and an out-bus, where one bus is primarily used for reads (input to the ALU) and the other for writes (output from the ALU), effectively dedicating the buses to roles to simplify control and reduce contention.

Two Bus Organizations

Two Bus Organizations

Three-Bus Organisation

The three-bus organisation adds further parallelism. Typically there are two output buses (for reading two source operands concurrently) and one input bus (for writing the ALU result). This allows:

• Two source operands to be presented to the ALU simultaneously from different registers.
• The ALU result to be placed on the input bus and written back to a destination register without waiting for the output buses to become free.
• Reduced busy-waiting compared with two-bus designs because the extra bus permits the result to be distributed while source buses are used for other reads.

Three Bus Organization

Comparative Advantages of Multiple-Bus Organisations

• Higher parallelism: Multiple buses allow concurrent transfers of operands and results, reducing wait cycles.
• Faster execution: Because several operands can be moved at once, the number of cycles per instruction typically decreases.
• Improved throughput: Multiple buses reduce contention and increase the effective data transfer bandwidth inside the CPU.
• Scalability: Designs with multiple buses make it easier to widen registers or add functional units for higher performance.

Practical Notes and Design Trade-offs

• Complexity vs cost: Adding buses increases hardware complexity and silicon area; designers must trade-off performance gains against cost and power consumption.
• Control complexity: Multiple buses require more sophisticated control logic to schedule transfers and avoid conflicts.
• Temporary buffers: Temporary registers or latches are often used to hold intermediate values while buses are busy; these buffers increase flexibility but also add hardware overhead.
• Microarchitecture choices: The choice between single-bus and multi-bus organisations depends on target performance, technology, and cost constraints. Contemporary processors often use register files and multi-ported access, which conceptually extend the same goals of multi-bus systems-reducing contention and supporting parallel operand access.

Summary

The ALU and the data path are central to CPU operation. Registers such as the PC, IR, MAR, MDR and GPRs store instructions, addresses, and operands that the ALU manipulates. The organisation of buses that interconnect these elements-one-bus, two-bus or three-bus-determines how many simultaneous transfers are possible and therefore strongly affects CPU performance. Multi-bus organisations improve parallelism and speed at the cost of increased hardware and control complexity. Understanding these trade-offs is fundamental to computer architecture and microarchitecture design.