Previous Year Questions- A-D and D-A Converters | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

Q1: An 8-bit ADC converts analog voltage in the range of 0 to +5 V to the corresponding digital code as per the conversion characteristics shown in figure. For V_in = 1,9922 V, which of the following digital output, given in hex is true? (2023)
(a) 64 H
(b) 65 H
(c) 66 H
(d) 67 H
Ans: (c)
Sol: Resolution =
Now, No. of step
For (101)₁₀ the analog input is less than 1.9922 V.
So, here we take (102)₁₀.
∴(102)₁₀ = 66H

Q2: A 2-bit flash Analog to Digital Converter (ADC) is given below. The input is 0 ≤ V_IN ≤ 3 Volts. The expression for the LSB of the output  B₀ as a Boolean function of X₂, X₁ and X₀ is  (SET-1(2016))
(a)
(b)
(c)
(d)
Ans: (a)
Sol: The input to digital circuuit is X₂, X₁, X₀ and output is B₁, B₀

Q3: A temperature in the range of -40°C to 55°C is to be measured with a resolution of 0.1°C. The minimum number of ADC bits required to get a matching dynamic range of the temperature sensor is (SET-1(2016))
(a) 8
(b) 10
(c) 12
(d) 14
Ans: (b)
Sol: Temperature range of −40°C to 55°C
So. Total range in 95°C
Since, resolution is 0.1°C
So, number of steps will be 950
To have 950 steps, we need at least 10 bits.

Q4: An 8-bit, unipolar Successive Approximation Register type ADC is used to convert 3.5 V to digital equivalent output. The reference voltage is +5 V. The output of the ADC, at the end of 3rd clock pulse after the start of conversion, is (SET-1(2015))
(a) 1010 0000
(b) 1000 0000
(c) 0000 0001
(d) 1000 0000
Ans: (a)
Sol: The reference voltage is 5 V.
The number of bits in ADC are 8.
So, the resolution will be = 5/(2⁸−1) = 5/255
The applied input is 3.5 V.
The succesive approximation ADC start working from the MSB so,
After one clock:
SAR will toggle it's MSB from 0 → 1. So, output of SAR will be 1000 0000.
After second clock:
SAR will toggle its 7th bit from  0 → 1 but 1100 0000 will result in value greater than 3.5. So, output of SAR after 2nd clock will be 1000 0000.
After third clock:
SAR will toggle it's 6th bit from 0 → 1 and output will be 1010 0000.

Q5: The Octal equivalent of HEX and number AB.CD is (2007)
(a) 253.314
(b) 253.632
(c) 526.314
(d) 526.632
Ans: (b)
Sol: Hex Number (AB.CD)
1010 1011 . 1100 1101
For finding its octal number, we can add one zero in both extreme and grouping.
010 101 011 . 110 011 010
Its equavalent octal number is (253.632)₈

Q6: It is required to design an anti-aliasing filter for an, 8 bit ADC. The filter is a first order RC filter with R = 1Ω and C = 1F. The ADC is designed to span a sinusoidal signal with peak to peak amplitude equal to the full scale range of the ADC.
What is the SNR (in dB) of the ADC ? Also find the frequency (in decades) at the filter output at which the filter attenuation just exceeds the SNR of the ADC. (2006)
(a) 50 dB, 2 decade
(b) 50 dB, 2.5 decade
(c) 60 dB, 2 decade
(d) 60 dB, 2.5 decade
Ans: (b)

Q7: A student has made a 3-bit binary down counter and connected to the R-2R ladder type DAC [Gain = (-1KΩ/2R)] as shown in figure to generate a staircase waveform. The output achieved is different as shown in figure. What could be the possible cause of this error ?  (2006)
(a) The resistance values are incorrect option.
(b) The counter is not working properly
(c) The connection from the counter of DAC is not proper
(d) The R and 2R resistance are interchanged
Ans: (c)
Sol: Initial stage of the counter =(111)₂ = (7)₁0
So output will be equal to 7 V.
Next state of counter =(110)₂ = (6)₁0
So output should be = 6 V
But output is 3 V that meansLSB of counter is connected to MSB of DAC and MSB of counter is connected to LSB of DAC.
Similarly next state oc counter = (101)₂ = (5)₁0
Input to DAC = (101)₂ = (5)₁0
So, output = 5V
When counter goes to (100)₂ then input to DAC = (001)₂ = (1)₁0
So output = 1 V
So connections are not proper.

Q8: The voltage comparator shown in figure can be used in the analog-to-digital conversion as (2004)
(a) a 1-bit quantizer
(b) a 2-bit quantizer
(c) a 4-bit quantizer
(d) a 8-bit quantizer
Ans: (a)
Sol: Even when V₁ > V₂, the (o/p) 'V0V0' is high and for the next case (V₁ < V₂) (o/p) is low.It is 1 bit quantizer. Since, it has two states which can be represented by 1 bit.

Q9: A sample-and-hold (S/H) circuit, having a holding capacitor of 0.1 nF, is used at the input of an ADC (analog-to-digital converter). The conversion time of the ADC is 1 μsec, and during this time, the capacitor should not lose more than 0.5% of the charge put across it during the sampling time. The maximum value of the input signal to the S/H circuit is 5V. The leakage current of the S/H circuit should be less than (2001)
(a) 2.5 mA
(b) 0.25 mA
(c) 25 mA
(d) 2.5 mA
Ans: (d)

Q10: Among the following four, the slowest ADC (analog-to-digital converter) is (2001)
(a) parallel comparator (i.e., flash) type
(b) successive approximation type
(c) integrating type
(d) counting type
Ans: (c)