Previous Year Questions- BJT, FET and their Biasing Circuits - 2 | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

Q17: Two perfectly matched silicon transistor are connected as shown in the figure assuming the β of the transistors to be very high and the forward voltage drop in diodes to be 0.7 V, the value of current I is (2008)
(a) 0 mA
(b) 3.6 mA
(c) 4.3 mA
(d) 5.7 mA
Ans: (b)
Sol: Since both transitor are perfectly matched,
So, V_BE1 = V_BE2
Since \beta for both are same, therefore
I_b1 = I_b2 = I_b
Applying KVL to loop as shown,
By KCL,
I_R = I_c+ 2I_b
≈ I_R (Because β is very large)

Q18: The common emitter forward current gain of the transistor shown is β_F = 100.  
The transistor is operating in (2007)
(a) Saturation region
(b) Cutoff region
(c) Reverse active region
(d) Forward active region
Ans: (d)
Sol: We assume BJT is in active region, applying KVL in base emitter circuit
10 − 0.7 = 1kΩ × I_c + 270 × I_b
= I_b(270 + 100k)
I_c(sat) > I_c(active)
∴ BJT is in active region.

Q19: Consider the circuit shown in figure. If the β of the transistor is 30 and I_CBO is 20 mA and the input voltage is +5 V, the transistor would be operating in (2006)
(a) saturation region
(b) active region
(c) breakdown region
(d) cut-off region
Ans: (b)
Sol: Assume BJT is in active Region and we neglect I_CBO,
as I_c(sat) > I_c(active)
BJT is in active region.

Q20: Assume that the threshold voltage of the N-channel MOSFET shown in figure is + 0.75 V. The output characteristics of the MOSFET are also shown
The voltage gain of the amplifier is (2005)
(a) +5
(b) -7.5
(c) +10
(d) -10
Ans: (d)
Sol: Since, r_d >> R
All current will pass through R
V_out = −g_mV_GSR
= −1 × 10⁻³ × 2 × 10⁻³ × 10 × 10⁻³
= −20mV
Volate gain

Q21:  Assume that the threshold voltage of the N-channel MOSFET shown in figure is + 0.75 V. The output characteristics of the MOSFET are also shown
The transconductance of the MOSFET is (2005)
(a) 0.75 ms
(b) 1 ms
(c) 2 ms
(d) 10 ms
Ans: (b)

Sol: 

Q22: The common emitter amplifier shown in the figure is biased using a 1 mA ideal current source. The approximate base current value is (2005)
(a) 0 μA
(b) 10 μA
(c) 100 μA
(d) 1000 μA
Ans: (b)

Sol: β = I_c/I_b
I_b =

Q23: Assume that the N-channel MOSFET shown in the figure is ideal, and that its threshold voltage is +1.0 V. The voltage V_ab between nodes a and b is: (2005)
(a) 5V
(b) 2V
(c) 1V
(d) 0V
Ans: (d)

Sol: MOSFET is N_channel. Gate through souce is so connected that MOSFET will be in enhance mode and so conductivity of the channel will be increased very much and effectively 'β' terminal act as short circuited, So,  V_ab = 0V.

Q24: The value of R for which the PMOS transistor in figure will be biased in linear region is (2004)
(a) 220 Ω
(b) 470 Ω
(c) 680 Ω
(d) 1200 Ω
Ans: (d)
Sol: Here
V_S = +4V
V_G = 0V
V_T = −1V
Therefore, V_SG = 4V
V_SD = V_S − V_D
= 4 − I_aR
Now for linear region of operation V_SD < (V_SG − V_T)
⇒ 4 − I_aR < (4 − 1)
⇒ I_a(R) > 1
⇒ 10⁻³ × R > 1
R > 1000Ω

Q25: The transconductance g_m of the transistor shown in figure is 10 mS. The value of the input resistance R_IN is (2004)
(a) 10.0 kΩ
(b) 8.3 kΩ
(c) 5.0 kΩ
(d) 2.5 kΩ
Ans: (d)
Sol: Input Resistance= 

But overall input resistance seen from source is
R_IN = 10 ∥ 10 ∥ 5 = 2.5kΩ

Q26: Two perfectly matched silicon transistor are connected as shown in figure. The value of the current I is (2004)
(a) 0 mA
(b) 2.3 mA
(c) 4.3 mA
(d) 7.3 mA
Ans: (c)
Sol: Both transistor are perfectly matched, hence
V_BE2 = V_BE1  
therefore, I_c1/I_c2 = exp[(V_BE1 − V_BE2)/V_T] = 1
Also 'β' is same.
Writing KCL at node B,
I_c + 2I_b − I_R = 0
I_c = βI_b
≈ I_R (Because β is very large)
Hence, I_c1 = I_c2 = I_R = 4.3mA  

Q27: For the n-channel enhancement MOSFET shown in figure, the threshold voltage V_th = 2 V. The drain current I_D of the MOSFET is 4 mA when the drain resistance R_D is 1 kΩ. If the value of R_D is increased to 4 kΩ, drain current I_D will become (2003)
(a) 2.8mA
(b) 2.0mA
(c) 1.4mA
(d) 1.0mA
Ans: (c)
Sol: I_D = K(V_GS − V_th)²
4 = K(6 − 2)²
∴ K = (1/4)mA/V²
V_GS = 10−4×1 = 6V
when R_D is increased to 4kΩ
V_GS = 10 − 4I_D
I_D = 1/4(10 − 4I_D − 2)²
4I_D = 16I²_D + 64 − 64I_D
16I²_D − 68I_D + 64 = 0
I_D = 2.84 mA, 1.4 mA
For MOSFET to be on, V_GS must be greater than V_th and this is possible only if
I_D = 1.4mA
If I_D = 2.84 mA
then V_GS become -ve and less than V_th so transistor will be off for this value which is not possible since V_DG = 0 ≥ − V_th.

Q28: In the circuit of figure, assume that the transistor has h_FE = 99 and V_BE = 0.7 V. The value of collector current I_C of the transistor is approximately (2003)
(a) [3.3/3.3] mA
(b) [3.3/(3.3 +.33)] mA
(c) [3.3/33] mA
(d) [3.3/(33 + 3.3)] mA
Ans: (b)
Sol: Using KVL in Base-emitter Loop
4 − 33 × I_b − 0.7 − 3.3 × 100I_b = 0(I_c = βI_b)

Q29: The variation of drain current with gate-to-source voltage (I_D - V_GS characteristic) of a MOSFET is shown in figure. The MOSFET is (2003)
(a) an n-channel depletion mode device
(b) an n-channel enhancement mode device
(c) an p-channel depletion mode device
(d) an p-channel enhancement mode device
Ans: (c)
Sol: This is the characteristics of a p-channel depletion mode device.

Q30: An n-channel JFET, having a pinch-off voltage (V_p) of -5 V, shows a transconductance (g_m) of 1 mA/V when the applied gate-to-source voltage (V_GS) is -3V. Its maximum transconductance (in mA/V) is (2001)
(a) 1.5
(b) 2
(c) 2.5
(d) 3
Ans: (c)
Sol: