Formula Sheet: Semiconductor Devices

PN Junction Diodes

Basic Diode Equations

Shockley Diode Equation: \[I_D = I_S \left(e^{\frac{V_D}{nV_T}} - 1\right)\]

• \(I_D\) = diode current (A)
• \(I_S\) = reverse saturation current (A), typically 10^-12 to 10^-15 A
• \(V_D\) = voltage across diode (V)
• \(n\) = ideality factor or emission coefficient (dimensionless), typically 1 to 2
• \(V_T\) = thermal voltage (V)

Thermal Voltage: \[V_T = \frac{kT}{q}\]

• \(k\) = Boltzmann's constant = 1.38 × 10^-23 J/K
• \(T\) = absolute temperature (K)
• \(q\) = electron charge = 1.60 × 10^-19 C
• At room temperature (T = 300 K): \(V_T\) ≈ 25.9 mV ≈ 26 mV

Simplified Diode Equation (for forward bias where \(V_D \gg V_T\)): \[I_D \approx I_S e^{\frac{V_D}{nV_T}}\]

Diode Resistance

Static (DC) Resistance: \[R_D = \frac{V_D}{I_D}\] Dynamic (AC or Small-Signal) Resistance: \[r_d = \frac{dV_D}{dI_D} = \frac{nV_T}{I_D}\]

• Also called incremental resistance
• For \(n = 1\): \(r_d = \frac{V_T}{I_D}\)
• At room temperature with \(n = 1\): \(r_d \approx \frac{26 \text{ mV}}{I_D}\)

Breakdown Voltage

Zener Breakdown: Occurs in heavily doped junctions at low voltages (typically < 5v)="" due="" to="" field="" ionization="">Avalanche Breakdown: Occurs in lightly doped junctions at higher voltages due to impact ionization

Junction Capacitance

Depletion Capacitance (Transition Capacitance): \[C_j = \frac{C_{j0}}{\left(1 - \frac{V_D}{V_{bi}}\right)^m}\]

• \(C_j\) = junction capacitance (F)
• \(C_{j0}\) = zero-bias junction capacitance (F)
• \(V_D\) = applied voltage (V), negative for reverse bias
• \(V_{bi}\) = built-in potential (V), typically 0.6-0.9 V
• \(m\) = grading coefficient (0.3-0.5 for typical junctions)

Diffusion Capacitance (for forward-biased diode): \[C_d = \frac{\tau_T I_D}{nV_T}\]

• \(C_d\) = diffusion capacitance (F)
• \(\tau_T\) = transit time (s)
• \(I_D\) = diode current (A)

Special Purpose Diodes

Zener Diode

Zener Diode in Regulation (Reverse Bias): \[V_Z \approx \text{constant for } I_Z \geq I_{Z,min}\] Dynamic Impedance: \[r_z = \frac{\Delta V_Z}{\Delta I_Z}\]

• \(r_z\) = dynamic resistance of Zener diode (Ω)
• Typically very small (few Ω to tens of Ω)

Schottky Diode

• Metal-semiconductor junction
• Lower forward voltage drop (0.2-0.4 V) compared to PN junction
• Faster switching due to majority carrier conduction
• No charge storage effect

Varactor Diode (Varicap)

Capacitance vs. Voltage: \[C_j = \frac{C_{j0}}{\left(1 + \frac{|V_R|}{V_{bi}}\right)^m}\]

• \(V_R\) = reverse bias voltage (V)
• Used for voltage-controlled capacitance

Bipolar Junction Transistors (BJT)

Current Relationships

Collector Current: \[I_C = \beta I_B = \alpha I_E\] Emitter Current: \[I_E = I_C + I_B\] Current Gain Relationships: \[\alpha = \frac{I_C}{I_E}\] \[\beta = \frac{I_C}{I_B}\] \[\alpha = \frac{\beta}{\beta + 1}\] \[\beta = \frac{\alpha}{1 - \alpha}\]

• \(\alpha\) = common-base current gain (typically 0.95-0.99)
• \(\beta\) = common-emitter current gain (typically 50-300)
• \(h_{FE}\) = DC current gain = \(\beta\)
• \(h_{fe}\) = AC (small-signal) current gain

Ebers-Moll Model

Active Mode (NPN): \[I_C = I_S e^{\frac{V_{BE}}{V_T}}\] Collector Current with Early Effect: \[I_C = I_S e^{\frac{V_{BE}}{V_T}} \left(1 + \frac{V_{CE}}{V_A}\right)\]

• \(V_A\) = Early voltage (V), typically 50-200 V
• \(V_{BE}\) = base-emitter voltage (V), typically 0.7 V for Si
• \(V_{CE}\) = collector-emitter voltage (V)

Operating Regions

Cutoff:

• Both junctions reverse-biased
• \(V_{BE} < 0.5\)="" v="">
• \(I_C \approx 0\), \(I_B \approx 0\)

Active (Normal Active):

• Base-emitter forward-biased, base-collector reverse-biased
• \(V_{BE} \approx 0.7\) V for Si, \(V_{BC} <>
• \(I_C = \beta I_B\)

Saturation:

• Both junctions forward-biased
• \(V_{BE} \approx 0.7-0.8\) V, \(V_{CE,sat} \approx 0.2\) V for Si
• \(I_C < \beta="">

Small-Signal Model (Hybrid-π Model)

Transconductance: \[g_m = \frac{I_C}{V_T}\]

• \(g_m\) = transconductance (S or mhos)
• At room temperature: \(g_m = \frac{I_C}{26 \text{ mV}}\)

Base-Emitter Resistance: \[r_\pi = \frac{\beta}{g_m} = \frac{\beta V_T}{I_C}\]

• \(r_\pi\) = small-signal input resistance (Ω)
• Also written as \(r_{be}\) or \(h_{ie}\)

Emitter Resistance: \[r_e = \frac{V_T}{I_E} \approx \frac{V_T}{I_C}\]

• \(r_e\) = intrinsic emitter resistance (Ω)
• At room temperature: \(r_e \approx \frac{26 \text{ mV}}{I_E}\)

Output Resistance: \[r_o = \frac{V_A + V_{CE}}{I_C} \approx \frac{V_A}{I_C}\]

• \(r_o\) = output resistance due to Early effect (Ω)

Common-Emitter Amplifier

Voltage Gain: \[A_v = -g_m R_C = -\frac{R_C}{r_e}\]

• \(R_C\) = collector load resistance (Ω)
• Negative sign indicates phase inversion

Input Resistance: \[R_{in} = r_\pi = \frac{\beta}{g_m}\] Output Resistance: \[R_{out} = R_C \parallel r_o \approx R_C\]

Common-Collector Amplifier (Emitter Follower)

Voltage Gain: \[A_v = \frac{g_m R_E}{1 + g_m R_E} \approx 1\]

• \(R_E\) = emitter load resistance (Ω)
• Voltage gain is slightly less than unity

Input Resistance: \[R_{in} = r_\pi + (\beta + 1)R_E \approx \beta R_E\] Output Resistance: \[R_{out} = R_E \parallel \left(\frac{r_\pi + R_S}{\beta + 1}\right) \approx \frac{1}{g_m}\]

• \(R_S\) = source resistance (Ω)

Common-Base Amplifier

Voltage Gain: \[A_v = g_m R_C\] Input Resistance: \[R_{in} = r_e = \frac{1}{g_m}\] Output Resistance: \[R_{out} = R_C\]

Field-Effect Transistors (FET)

JFET (Junction Field-Effect Transistor)

Drain Current (Shockley Equation): \[I_D = I_{DSS} \left(1 - \frac{V_{GS}}{V_P}\right)^2\]

• \(I_D\) = drain current (A)
• \(I_{DSS}\) = drain-source saturation current with \(V_{GS} = 0\) (A)
• \(V_{GS}\) = gate-source voltage (V)
• \(V_P\) = pinch-off voltage (V), negative for n-channel
• Valid in saturation region

Transconductance: \[g_m = \frac{2I_{DSS}}{|V_P|} \left(1 - \frac{V_{GS}}{V_P}\right) = \frac{2\sqrt{I_{DSS} I_D}}{|V_P|}\]

• \(g_m\) = transconductance (S)
• Also: \(g_m = g_{m0}\left(1 - \frac{V_{GS}}{V_P}\right)\) where \(g_{m0} = \frac{2I_{DSS}}{|V_P|}\)

Operating Regions:

• Cutoff: \(V_{GS} \leq V_P\), \(I_D = 0\)
• Ohmic (Triode): \(V_{DS} < v_{gs}="" -="">
• Saturation (Active): \(V_{DS} \geq V_{GS} - V_P\)

MOSFET (Metal-Oxide-Semiconductor FET)

Enhancement-Mode MOSFET Drain Current (Saturation Region): \[I_D = \frac{1}{2} \mu_n C_{ox} \frac{W}{L} (V_{GS} - V_t)^2\] Alternative Form: \[I_D = \frac{k_n}{2} (V_{GS} - V_t)^2\] Including Channel-Length Modulation: \[I_D = \frac{k_n}{2} (V_{GS} - V_t)^2 (1 + \lambda V_{DS})\]

• \(\mu_n\) = electron mobility (cm²/V·s)
• \(C_{ox}\) = oxide capacitance per unit area (F/cm²)
• \(W\) = channel width (μm or cm)
• \(L\) = channel length (μm or cm)
• \(V_t\) = threshold voltage (V)
• \(k_n\) = process transconductance parameter = \(\mu_n C_{ox} \frac{W}{L}\) (A/V²)
• \(\lambda\) = channel-length modulation parameter (V^-1)

Alternative Notation (NCEES): \[I_D = K(V_{GS} - V_t)^2\]

• \(K\) = conduction parameter = \(\frac{k_n}{2}\) (A/V²)

Triode (Linear) Region: \[I_D = k_n \left[(V_{GS} - V_t)V_{DS} - \frac{V_{DS}^2}{2}\right]\]

• Valid when \(V_{DS} < v_{gs}="" -="">

Small-Signal Transconductance: \[g_m = \frac{\partial I_D}{\partial V_{GS}} = k_n(V_{GS} - V_t) = \sqrt{2k_n I_D}\] Output Resistance: \[r_o = \frac{1}{\lambda I_D}\]

• \(r_o\) = output resistance (Ω)

MOSFET Operating Regions

Cutoff:

• \(V_{GS} <>
• \(I_D = 0\)

Triode (Linear/Ohmic):

• \(V_{GS} > V_t\) and \(V_{DS} < v_{gs}="" -="">
• Channel not pinched off

Saturation (Active):

• \(V_{GS} > V_t\) and \(V_{DS} \geq V_{GS} - V_t\)
• Channel pinched off
• Used for amplification

Common-Source Amplifier (MOSFET)

Voltage Gain: \[A_v = -g_m R_D\]

• \(R_D\) = drain load resistance (Ω)

With Channel-Length Modulation: \[A_v = -g_m (R_D \parallel r_o)\] Input Resistance: \[R_{in} = R_G\]

• \(R_G\) = gate biasing resistance (Ω)
• Ideally infinite due to gate insulation

Output Resistance: \[R_{out} = R_D \parallel r_o\]

Common-Drain Amplifier (Source Follower)

Voltage Gain: \[A_v = \frac{g_m R_S}{1 + g_m R_S} < 1\]="">

• \(R_S\) = source load resistance (Ω)

Input Resistance: \[R_{in} = R_G\] Output Resistance: \[R_{out} = \frac{1}{g_m} \parallel R_S\]

CMOS Inverter

Complementary Pair: n-channel MOSFET (NMOS) and p-channel MOSFET (PMOS) in series Static Power Dissipation: \[P_{static} \approx 0\]

• Only one transistor conducts in steady state

Dynamic Power Dissipation: \[P_{dynamic} = C_L V_{DD}^2 f\]

• \(C_L\) = load capacitance (F)
• \(V_{DD}\) = supply voltage (V)
• \(f\) = switching frequency (Hz)

Thyristors

Silicon-Controlled Rectifier (SCR)

Four-Layer PNPN Device Latching Current: Minimum anode current to maintain conduction after gate trigger is removed Holding Current: Minimum anode current to keep SCR in ON state Gate Trigger Condition:

• Anode positive with respect to cathode
• Sufficient gate current \(I_G\) applied

Turn-off Methods:

• Natural commutation (AC circuits)
• Forced commutation (DC circuits)
• Anode current must drop below holding current

DIAC and TRIAC

DIAC: Bidirectional diode thyristor, conducts in both directions after breakover voltage TRIAC: Bidirectional SCR, can be triggered in either direction

Optoelectronic Devices

Photodiode

Photocurrent: \[I_{ph} = \eta \frac{qP_o}{h\nu} = \eta \frac{q\lambda P_o}{hc}\]

• \(I_{ph}\) = photocurrent (A)
• \(\eta\) = quantum efficiency (dimensionless)
• \(P_o\) = optical power (W)
• \(h\) = Planck's constant = 6.626 × 10^-34 J·s
• \(\nu\) = frequency of light (Hz)
• \(\lambda\) = wavelength of light (m)
• \(c\) = speed of light = 3 × 10⁸ m/s

Responsivity: \[R = \frac{I_{ph}}{P_o}\]

• \(R\) = responsivity (A/W)

Light Emitting Diode (LED)

Photon Energy: \[E = h\nu = \frac{hc}{\lambda}\] Wavelength from Bandgap: \[\lambda = \frac{hc}{E_g}\]

• \(E_g\) = bandgap energy (eV or J)

Approximate Wavelength (in μm) from Bandgap (in eV): \[\lambda (\mu m) \approx \frac{1.24}{E_g (eV)}\]

Solar Cell

Current-Voltage Relationship: \[I = I_L - I_D = I_L - I_S\left(e^{\frac{V}{nV_T}} - 1\right)\]

• \(I_L\) = light-generated current (A)
• \(I_D\) = diode current (A)

Short-Circuit Current: \[I_{SC} = I_L\]

• Current when \(V = 0\)

Open-Circuit Voltage: \[V_{OC} = nV_T \ln\left(\frac{I_L}{I_S} + 1\right)\]

• Voltage when \(I = 0\)

Fill Factor: \[FF = \frac{V_{mp} \times I_{mp}}{V_{OC} \times I_{SC}}\]

• \(V_{mp}\) = voltage at maximum power point (V)
• \(I_{mp}\) = current at maximum power point (A)

Efficiency: \[\eta = \frac{P_{out}}{P_{in}} = \frac{V_{mp} \times I_{mp}}{P_{in}} = \frac{FF \times V_{OC} \times I_{SC}}{P_{in}}\]

• \(P_{in}\) = incident optical power (W)

Semiconductor Physics

Intrinsic Carrier Concentration

Mass Action Law: \[n \cdot p = n_i^2\]

• \(n\) = electron concentration (cm^-3)
• \(p\) = hole concentration (cm^-3)
• \(n_i\) = intrinsic carrier concentration (cm^-3)

Intrinsic Carrier Concentration: \[n_i^2 = N_C N_V e^{-\frac{E_g}{kT}}\]

• \(N_C\) = effective density of states in conduction band (cm^-3)
• \(N_V\) = effective density of states in valence band (cm^-3)
• \(E_g\) = bandgap energy (eV or J)

Silicon at Room Temperature: \[n_i \approx 1.5 \times 10^{10} \text{ cm}^{-3}\]

Doped Semiconductors

n-type (Donor Doping): \[n \approx N_D\] \[p \approx \frac{n_i^2}{N_D}\]

• \(N_D\) = donor concentration (cm^-3)

p-type (Acceptor Doping): \[p \approx N_A\] \[n \approx \frac{n_i^2}{N_A}\]

• \(N_A\) = acceptor concentration (cm^-3)

Conductivity

Conductivity: \[\sigma = q(n\mu_n + p\mu_p)\]

• \(\sigma\) = electrical conductivity (S/cm or Ω^-1·cm^-1)
• \(\mu_n\) = electron mobility (cm²/V·s)
• \(\mu_p\) = hole mobility (cm²/V·s)

Resistivity: \[\rho = \frac{1}{\sigma}\]

• \(\rho\) = resistivity (Ω·cm)

Drift and Diffusion

Drift Current Density: \[J_{drift} = q(n\mu_n + p\mu_p)E\]

• \(J_{drift}\) = drift current density (A/cm²)
• \(E\) = electric field (V/cm)

Diffusion Current Density: \[J_{diff,n} = qD_n \frac{dn}{dx}\] \[J_{diff,p} = -qD_p \frac{dp}{dx}\]

• \(D_n\) = electron diffusion coefficient (cm²/s)
• \(D_p\) = hole diffusion coefficient (cm²/s)

Einstein Relation: \[\frac{D_n}{\mu_n} = \frac{D_p}{\mu_p} = V_T = \frac{kT}{q}\]

Built-in Potential

PN Junction Built-in Potential: \[V_{bi} = V_T \ln\left(\frac{N_A N_D}{n_i^2}\right)\]

• \(V_{bi}\) = built-in potential (V)
• At room temperature: \(V_{bi} = 0.026 \ln\left(\frac{N_A N_D}{n_i^2}\right)\)

Depletion Width

Total Depletion Width: \[W = \sqrt{\frac{2\epsilon_s}{q}\left(\frac{N_A + N_D}{N_A N_D}\right)(V_{bi} - V_A)}\]

• \(W\) = total depletion width (cm)
• \(\epsilon_s\) = semiconductor permittivity (F/cm)
• \(V_A\) = applied voltage (V), positive for forward bias, negative for reverse bias

One-Sided Abrupt Junction (N_A >> N_D): \[W \approx \sqrt{\frac{2\epsilon_s (V_{bi} - V_A)}{qN_D}}\]

Power Devices

Power Diode

Reverse Recovery Time: Time required for diode to turn off after switching from forward to reverse bias Forward Recovery Time: Time required for forward voltage to stabilize after turn-on

Power MOSFET

On-Resistance: \[R_{DS(on)} = \frac{V_{DS}}{I_D}\]

• \(R_{DS(on)}\) = drain-source on-resistance (Ω)
• Key parameter for power loss calculation

Switching Power Loss: \[P_{sw} = \frac{1}{2}V_{DS} I_D (t_r + t_f) f_{sw}\]

• \(t_r\) = rise time (s)
• \(t_f\) = fall time (s)
• \(f_{sw}\) = switching frequency (Hz)

Conduction Power Loss: \[P_{cond} = I_D^2 R_{DS(on)}\]

IGBT (Insulated Gate Bipolar Transistor)

• Combines high input impedance of MOSFET with low on-state losses of BJT
• Used for high-power, high-voltage applications
• Gate-controlled like MOSFET
• Collector-emitter terminals like BJT

Charge Storage and Switching

Storage Time

Storage Time in BJT: \[t_s = \tau_s \ln\left(\frac{I_{B1} + I_{B2}}{I_{B2}}\right)\]

• \(t_s\) = storage time (s)
• \(\tau_s\) = storage time constant (s)
• \(I_{B1}\) = forward base current (A)
• \(I_{B2}\) = reverse base current magnitude (A)

Transit Time

Cutoff Frequency: \[f_T = \frac{g_m}{2\pi(C_{gs} + C_{gd})}\]

• \(f_T\) = unity gain frequency (Hz)
• \(C_{gs}\) = gate-source capacitance (F)
• \(C_{gd}\) = gate-drain capacitance (F)

For BJT: \[f_T = \frac{g_m}{2\pi C_\pi}\]

• \(C_\pi\) = base-emitter capacitance (F)

Device Ratings and Limits

Safe Operating Area (SOA)

Power Dissipation Limit: \[P_D = V_{CE} \times I_C \leq P_{D,max}\]

• \(P_{D,max}\) = maximum power dissipation (W)

Junction Temperature: \[T_J = T_A + P_D \times \theta_{JA}\]

• \(T_J\) = junction temperature (°C)
• \(T_A\) = ambient temperature (°C)
• \(\theta_{JA}\) = thermal resistance junction-to-ambient (°C/W)

With Heat Sink: \[T_J = T_A + P_D(\theta_{JC} + \theta_{CS} + \theta_{SA})\]

• \(\theta_{JC}\) = thermal resistance junction-to-case (°C/W)
• \(\theta_{CS}\) = thermal resistance case-to-sink (°C/W)
• \(\theta_{SA}\) = thermal resistance sink-to-ambient (°C/W)

Maximum Ratings

• \(V_{CEO,max}\) = maximum collector-emitter voltage with base open
• \(I_{C,max}\) = maximum collector current
• \(P_{D,max}\) = maximum power dissipation
• \(T_{J,max}\) = maximum junction temperature

Breakdown Mechanisms

Avalanche Breakdown

Breakdown Voltage (Approximation): \[V_{BR} \propto \frac{E_g^{3/2}}{N}\]

• \(V_{BR}\) = breakdown voltage (V)
• \(N\) = doping concentration (cm^-3)
• Higher doping leads to lower breakdown voltage

Punch-Through

• Depletion region extends through entire base or drift region
• Limits reverse voltage capability

Miller Effect

Miller Capacitance: \[C_M = C_{gd}(1 + |A_v|)\]

• \(C_M\) = Miller capacitance reflected to input (F)
• \(C_{gd}\) = gate-drain (or base-collector) capacitance (F)
• \(A_v\) = voltage gain magnitude

Effective Input Capacitance: \[C_{in} = C_{gs} + C_{gd}(1 + |A_v|)\]