CODE GENERATION
The final phase in compiler model is the code generator. It takes as input an intermediate representation of the source program and produces as output an equivalent target program. The code generation techniques presented below can be used whether or not an optimizing phase occurs before code generation.
ISSUES IN THE DESIGN OF A CODE GENERATOR
The following issues arise during the code generation phase:
1. Input to code generator
2. Target program
3. Memory management
4. Instruction selection
5. Register allocation
6. Evaluation order
1. Input to code generator:
a. Linear representation such as postfix notation
b. Three address representation such as quadruples
c. Virtual machine representation such as stack machine code
d. Graphical representations such as syntax trees and dags.
e. Prior to code generation, the front end must be scanned, parsed and translated into intermediate representation along with necessary type checking. Therefore, input to code generation is assumed to be error-free.
f.
2. Target program:
- It can be placed in a fixed memory location and can be executed immediately. b. Relocatable machine language
- It allows subprograms to be compiled separately.
c. Assembly language
- Code generation is made easier.
3. Memory management:
j:gotoigenerates jump instruction as follows:
* if i < j, a backward jump instruction with target address equal to location of code for quadruple i is generated.
* if i > j, the jump is forward. We must store on a list for quadruple i the location of the first machine instruction generated for quadruple j. When i is processed, the machine locations for all instructions that forward jumps to i are filled.
4. Instruction selection:
a:=b+c
d:=a+e (a)
MOV b,R0
ADD c,R0
MOV R0,a (b)
MOV a,R0
ADD e,R0
MOV R0,d
5. Register allocation
1. Register allocation - the set of variables that will reside in registers at a point in the program is selected.
2. Register assignment - the specific register that a value picked•
3. Certain machine requires even-odd register pairs for some operands and results. For example , consider the division instruction of the form :D x, y
where, x - dividend even register in even/odd register pair y-divisor
even register holds the remainder
odd register holds the quotient
6. Evaluation order
Some computation orders require fewer registers to hold intermediate results than others.
1. What is a code generator? |
2. What are some issues that can arise in the design of a code generator? |
3. How can code generators handle complex or ambiguous input specifications? |
4. How can code generators ensure maintainability and extensibility? |
5. How can code generators optimize performance and efficiency? |
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