Main Memory Organization Stored Program - Computer Architecture & Organisation (CAO)

Main Memory Organization: Stored Program

Stored-program concept is the foundational idea on which present-day digital computers are built. In this concept both program instructions and data are kept in the same addressable memory so that the Central Processing Unit (CPU) can fetch instructions and data directly from memory during program execution. This approach allows programs to be easily modified, loaded, and executed under program control.

The stored-program idea was formalised by John von Neumann and his colleagues in the mid-1940s. In 1946 they began the design of a stored-program computer at the Institute for Advanced Study, Princeton. This machine is commonly referred to as the IAS computer.

IAS Computer: Basic Structure and Components

The IAS computer organised the system into three basic units. The structure of the IAS computer is shown below.

• Central Processing Unit (CPU)
• Main Memory Unit
• Input/Output Devices

Central Processing Unit

The CPU is the primary unit responsible for carrying out computations and controlling the sequence of operations. In the IAS design the CPU is logically divided into:

• Data processing unit - contains high-speed registers and the arithmetic-logic unit (ALU) that perform arithmetic and logical operations.
• Program control unit - contains control circuits that fetch instructions from memory, decode the operation codes (opcodes), sequence micro-operations, and generate control signals for the rest of the system.

High-speed registers in the data processing unit provide temporary storage of instructions, memory addresses and data while they are being manipulated by the ALU.

Main Memory Unit

The main memory stores both program instructions and the data on which those instructions operate. Main memory is made up of a large number of storage cells; each cell stores a fixed amount of information (a word) and each cell is accessible by a unique address. Memory organisation describes how words are addressed, how many bits comprise a word (word size), and how memory is accessed.

Key concepts and components related to main memory:

• Addressability - memory can be byte-addressable or word-addressable depending on the architecture.
• Memory Address Register (MAR) - holds the address of the memory location to be read from or written to.
• Memory Buffer Register (MBR) or Memory Data Register (MDR) - temporarily holds data transferred to or from memory.
• Volatility - main memory (RAM) is typically volatile: contents are lost when power is removed; non-volatile memory (ROM, PROM, etc.) retains contents without power.
• Types of main memory - examples include RAM (Random Access Memory: SRAM, DRAM) and ROM (Read-Only Memory) used for firmware or bootstrap code.

Input / Output Devices

I/O devices provide the interface between the computer and the external world. They transfer programs, data and results between the computer and users or other systems and are controlled by the CPU using specific I/O instructions or memory-mapped I/O techniques.

Execution Model: Fetch-Decode-Execute (Stored-Program Operation)

The stored-program organisation allows the CPU to execute instructions stored in memory by repeating a cycle commonly called fetch-decode-execute. The cycle is:

1. Fetch the instruction from memory into the Instruction Register (IR).
2. Decode the instruction to determine the operation and the operands.
3. Fetch any required operand(s) from registers or memory.
4. Execute the operation in the ALU or other functional unit.
5. Store the result back into a register or memory, and update the Program Counter (PC) to point to the next instruction.

Registers Involved in Instruction Execution

• Program Counter (PC) - holds the address of the next instruction to fetch.
• Instruction Register (IR) - holds the currently fetched instruction.
• Memory Address Register (MAR) - holds the address for a memory access.
• Memory Buffer Register (MBR) / Memory Data Register (MDR) - holds data read from or to be written to memory.
• Accumulator (AC) - an example of a working register used by many early machines (including IAS) for arithmetic and logical operations.

Memory Organisation and Practical Considerations

Design of main memory and its organisation affect performance and programming model. Important considerations include:

• Access time - the time required to read or write a memory cell (lower is better for performance).
• Capacity - total number of addressable words or bytes in main memory.
• Word size - number of bits in a memory word; influences instruction encoding and datapath width.
• Endianness - byte order within multi-byte words (big-endian or little-endian).
• Memory hierarchy - registers → cache → main memory → secondary storage; faster, smaller memories are placed closer to the CPU to improve effective performance.

Example: A Simple Instruction Flow

Consider a simple load instruction that places a memory word into the accumulator. The steps the CPU performs are:

1. The CPU places the address of the instruction (from PC) into MAR and issues a read to memory.
2. The memory returns the instruction to MBR; the CPU transfers it to IR.
3. The PC is incremented so it points to the next instruction.
4. The instruction in IR is decoded; the address of the operand is placed into MAR.
5. The CPU issues a read; the data from memory is placed into MBR and then moved into the AC (accumulator).
6. The instruction completes and the CPU proceeds to fetch the next instruction pointed to by PC.

Summary

The stored-program organisation pioneered by von Neumann and implemented in the IAS design places both instructions and data in main memory and lets the CPU fetch, decode and execute instructions sequentially under program control. Understanding the roles of the CPU, main memory and registers (PC, IR, MAR, MBR, AC) together with the fetch-decode-execute cycle is essential to grasp how modern computers operate at the architectural level.