CPU Structure & Function - Computer Architecture & Organisation (CAO) -

Table of Contents
1. Responsibilities of the CPU
2. Major Components of the CPU
3. Register Organization
4. Control and Status Registers
5. The Instruction Cycle
6. Data Flow and Typical Registers Used
7. Practical notes and examples
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CPU Structure and Function  CPU Structure and Function Processor Organization

Responsibilities of the CPU

• Fetch instructions from memory in sequence.
• Interpret instructions to determine required actions (decoding the opcode).
• Fetch data operands from registers, cache, or main memory as required by instructions.
• Process data by performing arithmetic, logical and control operations.
• Write data back to registers, cache or main memory after processing.

To perform these operations quickly and reliably, the CPU contains a small amount of very fast internal memory called registers, and several functional units that cooperate under the direction of the control unit.

Fig: Internal Structure of the CPU

Major Components of the CPU

• Arithmetic and Logic Unit (ALU) - performs arithmetic operations (addition, subtraction, multiplication, division where supported) and logical operations (AND, OR, NOT, XOR, comparisons). The ALU is the principal execution unit for data computation.
• Control Unit (CU) - coordinates and controls the movement of data and instructions into, out of and within the CPU. The CU fetches instructions, decodes them, issues control signals to other CPU components and coordinates ALU activity and memory/I/O transfers.
• Registers - very fast storage locations inside the CPU used to hold instructions, addresses, operands, intermediate results and status information.
• Buses and Interfaces - address, data and control lines that connect the CPU with memory and I/O devices; the CU drives control lines for memory reads/writes and I/O operations.

Register Organization

Registers occupy the top position in the memory hierarchy and are critical to instruction execution and performance. Registers fall into two broad classes:

• User-visible registers - available to the programmer (via assembly language or compiler-generated code) for holding operands, addresses and intermediate values. Efficient use of these registers reduces references to slower main memory.
• Control and status registers - used by the control unit and operating system to manage CPU operation, instruction flow and exceptional conditions (interrupts, traps).

User-Visible Registers - categories and uses

• General-purpose registers - used for a variety of operations; compilers allocate these to hold temporary values and variables.
• Data registers - store numeric or logical data values.
• Address registers - hold memory addresses used for load/store and memory reference instructions.
• Segment pointers - hold base addresses of segments (in segmented memory architectures).
• Index registers - used for indexed addressing and iteration; some architectures support automatic indexing on memory reference.
• Stack Pointer (SP) - points to the top of the stack; push and pop instructions implicitly use the stack pointer, so explicit operand fields are unnecessary for these operations.
• Condition Codes / Flags - small registers (or bits within a status register) that capture results of arithmetic and logical operations (for example: zero, sign, carry, overflow).

Design issues for user-visible registers

• Specialised vs general-purpose registers - specialised registers (dedicated use) let instruction encodings omit register specifiers for some operands (saving bits), while general-purpose registers increase flexibility for compilers and programmers. Modern designs often balance both approaches.
• Number of registers - more registers can improve performance by reducing memory traffic, but require larger instruction fields to encode register operands. Typical conventional designs provide 8-32 registers; RISC philosophies may use many more registers with different tradeoffs.
• Register width (length) - address registers must be wide enough to hold the largest possible memory address; data registers should accommodate the widest data type commonly used. Some architectures allow pairing two registers to form double-width registers for large numeric types.
• Saving and restoring flag/condition state - some CPUs automatically save and restore condition flags on subroutine calls/returns; others require explicit save/restore instructions. The design choice affects calling conventions and interrupt handling complexity.

Control and Status Registers

• Registers essential to instruction execution - the following are typically present in some form in most CPU designs:
  • Program Counter (PC) - holds the address of the next instruction to be fetched.
  • Instruction Register (IR) - contains the instruction currently being executed (usually the decoded or fetched opcode and operand specifiers).
  • Memory Address Register (MAR) - holds the memory address to be accessed and is usually connected to the address lines of the memory bus.
  • Memory Buffer Register (MBR) - holds the data read from or to be written to memory and is usually connected to the memory data lines.
• Program Status Word (PSW) - a grouped status/control register that typically contains important condition and control fields. Common flags and fields include:
  • Sign - sign bit of last arithmetic result.
  • Zero - set when the last arithmetic or logical result was zero.
  • Carry - set if the last arithmetic operation produced a carry out (or borrow) from the most significant bit.
  • Equal - set when comparison operation detects equality (some architectures use Zero flag for this purpose).
  • Overflow - set if the last signed arithmetic result produced overflow.
  • Interrupt enable/disable - controls whether maskable interrupts are serviced.
  • Supervisor / Privilege - indicates whether the CPU is executing in user or privileged (supervisor/kernel) mode.
• Other optional control registers - depending on architecture and OS support:
  • Pointer to OS-maintained control block (for process management).
  • Interrupt vector or pointer to interrupt table.
  • System stack pointer (used in kernel mode).
  • Page table base pointer (for virtual memory translation).
  • I/O control and status registers for device interfacing.
• Design tradeoffs - architecture designers decide how much control information to place in CPU registers versus in main memory structures; moving frequently used control information into registers speeds access at the expense of increased register file complexity.

The Instruction Cycle

The instruction cycle is the repeating sequence of steps a CPU performs to execute programs. At a simple level, each instruction goes through these sub-cycles:

1. Fetch - read the next instruction from memory into the CPU.
2. Decode/Execute - interpret the opcode and perform the indicated operation; this often includes reading or writing data and invoking the ALU.
3. Interrupt handling - if an interrupt is pending and interrupts are enabled, the CPU saves the current state and transfers control to the interrupt service routine; after servicing, normal execution resumes.

The Indirect Cycle

Some addressing modes require an additional sub-cycle to obtain the effective address or operand. This is called the indirect cycle and may involve one or more memory accesses or simple arithmetic (indexing) to compute the actual operand address.

• The indirect cycle may be as simple as an extra memory read to fetch an address stored in memory, or it may require arithmetic (for example, base + index) before the final memory access.

Data Flow and Typical Registers Used

Actual data flow depends on CPU design. A typical simple CPU uses the following registers to implement fetch/indirect/execute cycles: MAR, MBR, PC, IR and various general purpose registers.

Fetch cycle - typical sequence of actions

• PC contains the address of the next instruction to be fetched.
• The address from the PC is transferred to the MAR, and placed on the address bus.
• The control unit issues a memory read request.
• The memory returns the instruction word on the data bus; the result is loaded into the MBR.
• The instruction in the MBR is moved to the IR for decoding and execution.
• Meanwhile the PC is incremented so that it points to the next instruction (or adjusted by control logic for branch/interrupt operations).

Indirect cycle - typical sequence

• After the initial fetch, the control unit decodes the IR.
• If the instruction specifies indirect addressing, the rightmost n bits or the address field in the MBR are transferred to the MAR.
• The control unit issues another memory read so that the memory reference (the effective address or operand address) is fetched into the MBR.

Execute cycle - general observations

The execute cycle is not uniform; its actions depend on the specific instruction in the IR. Possible actions include:

• Transferring data among registers.
• Accessing memory or I/O for reads or writes.
• Invoking the ALU to perform arithmetic or logical operations.
• Changing the PC for control transfer instructions (jumps, branches, calls, returns).

Interrupt cycle - typical sequence

• If an interrupt is recognised, the current PC (and often other state like PSW) must be saved so the interrupted program can resume after the interrupt service routine completes.
• The PC value is moved to the MBR and written to memory (commonly onto the process stack); the address to store it is placed in the MAR (for example, the system SP may be adjusted and used).
• The PC is loaded with the address of the interrupt service routine so the next fetch will begin executing the interrupt handler.

Practical notes and examples

• Many modern CPUs use pipelining to overlap fetch, decode and execute phases of different instructions; the basic cycles described above are still conceptually useful but are implemented concurrently across instructions in a pipeline.
• Registers such as the PC, IR, MAR and MBR are central to implementing the data flow between CPU and memory and are often tied directly to the system bus lines.
• Stack operations (push/pop) implicitly use the SP. For example, pushing a register value typically decrements the SP and writes the value to the memory address now pointed to by SP; popping reads from SP and then increments SP.
• Condition flags in the PSW are used by conditional branch instructions; a compare instruction sets flags which subsequent branch instructions test.
• Operating systems rely on control/status registers (such as privilege and interrupt enable bits) to implement context switching, interrupt masking and protection between user and kernel modes.

Summary

The CPU organises computation through a combination of the ALU, control unit and a bank of registers. Instruction execution proceeds through fetch, (possible) indirect, execute and interrupt handling sub-cycles using registers such as PC, IR, MAR and MBR. Register design (number, length and specialisation) and placement of control information are key architectural decisions that affect performance and OS support. Understanding the data flow through these components is essential for studying computer architecture and for designing or optimising programs at the machine level.