Arithmetic & Logic Unit - Computer Architecture & Organisation (CAO) -

Arithmetic and Logic Unit
The ALU (Arithmetic and Logic Unit) is the combinational circuit within a processor that actually performs the arithmetic and logical operations on data. All other major elements of a computer system - the control unit, registers, memory and I/O - exist primarily to deliver operands to the ALU, to provide control signals that select the operation, and to receive and store the results produced by the ALU. Modern ALUs and the surrounding processor circuitry are implemented with simple digital logic devices that store binary digits and implement Boolean functions.

ALU and Processor Interconnection

Data are presented to the ALU via processor registers. The result of an ALU operation is stored back into a register. These registers are temporary storage locations inside the processor; they are connected to the ALU by data paths (buses) and by control signals that allow data transfer. The ALU also produces a set of status flags (condition codes) as outcomes of operations; these flags are stored in special registers (flag register or status register) and are used by the control unit and by conditional instructions.

The control unit provides timing and control signals to the ALU to select the operation and to move data into and out of the ALU. Common flags set by the ALU include the Zero flag (result is zero), Carry flag (unsigned overflow or borrow), Sign flag (most-significant-bit of result for two's-complement interpretation), and Overflow flag (signed arithmetic overflow). The exact set of flags and their meanings are implementation-dependent, but these four are standard in many processor families.

Design Stages of an ALU

The design of an ALU is commonly described in three stages:

• Design the arithmetic section
• Design the logical section
• Combine the two sections and provide selection/decoder logic to choose among operations

Arithmetic Section

The basic building block of the arithmetic section is the full adder. A full adder implements the addition of two single bits and an input carry bit, producing a sum bit and a carry-out bit. N-bit addition is obtained by connecting N full adders in cascade to form a parallel (ripple-carry) adder. By controlling the inputs to the parallel adder (for example, by selectively inverting one operand and by providing an initial carry-in), the same hardware can perform a variety of arithmetic operations such as addition, subtraction (by two's complement), increment and decrement.

A single full adder implements the following Boolean expressions for sum and carry:

Using a parallel adder of n bits, commonly used arithmetic micro-operations include:

• Add: R = A + B
• Subtract: R = A - B (implemented as A + two's complement of B)
• Add with carry: R = A + B + C_in
• Increment/Decrement: R = A + 1 or R = A - 1

Subtraction using two's complement is implemented by inverting each bit of B and adding 1. In hardware the inversion of B and the addition of the initial carry-in can be controlled by selection lines so that the same adder performs both addition and subtraction. For example, to compute A - B:

where \( \overline{B} \) is the bitwise NOT of B, and the +1 is provided by setting the initial carry-in to 1.

Logical Section

The logical section produces bitwise logical micro-operations such as AND, OR, XOR and NOT. Each bit position is processed by a small combinational network of gates. A common implementation is to provide each logical function in parallel and then select the desired function output by a multiplexer (MUX).

A typical single-bit logical unit contains gates to compute:

• AND: \( A \cdot B \)
• OR: \( A + B \)
• XOR: \( A \oplus B \)
• NOT/A complement (often applied to a single operand): \( \overline{A} \)

The multiplexer selects which of these gate outputs will appear at the logical-unit output depending on the logic function selection inputs. The logical unit is then replicated for each bit of the operands to form an n-bit logical unit.

Combining Arithmetic and Logical Sections

Both arithmetic and logical outputs must be available so that the ALU can perform either kind of operation under control of the instruction decoder or control unit. The outputs of the arithmetic block and the logical block are fed into a final stage - commonly a multiplexer - that selects which block's output becomes the ALU result, denoted here as the G output lines for n bits.

The ALU uses a set of selection lines to determine the specific operation. A typical organisation uses a mode select line to distinguish arithmetic from logical operations, and additional function select lines to choose the particular operation within that mode. For example, with three selection lines S₂, S₁ and S₀, the ALU might use S₂ = 0 to indicate arithmetic mode and S₂ = 1 to indicate logical mode, while S₁ and S₀ select the precise operation in that mode. Exact encodings vary between designs; the important design principle is that a small decoder maps the selection lines to unique operations.

When the arithmetic and logical outputs are combined, the ALU also drives the status flags. Typical flag behaviours are:

• Zero flag: set when the ALU result is all zeros.
• Carry flag: set when an unsigned carry-out (or borrow in subtraction) occurs from the most-significant bit.
• Sign flag: set to the most-significant bit of the result (used for two's-complement signed results).
• Overflow flag: set when signed arithmetic produces a result outside the representable range (for example, adding two positive numbers yields a negative result in two's complement).

Practical Points, Examples and Considerations

Designers must consider the following points when creating an ALU for a processor:

• Propagation delay: the ripple-carry adder is simple but its carry ripple produces linear delay with bit width. Faster adders (carry-lookahead, carry-skip, carry-select) are used for high performance.
• Function set: choose a set of arithmetic and logic micro-operations required by the instruction set; supporting a small set of well-chosen functions simplifies the ALU.
• Bit-slicing: ALUs are often implemented with repeatable bit-slice units that can be chained to form 8-, 16-, 32- or 64-bit ALUs.
• Power and area: trade-offs between complexity (more functions, faster adders) and silicon area and power consumption.
• Flags and instruction semantics: exactly which flags are generated and when affects the behaviour of conditional instructions and must be precisely defined.

Example: To perform a 4-bit subtraction A - B using a 4-bit ripple-carry adder configured for two's-complement subtraction:

Invert all bits of B to form \( \overline{B} \), set initial carry-in \( C_{in} = 1 \), and compute \( A + \overline{B} + 1 \). The carry-out and overflow flags are then examined to determine unsigned carry/borrow and signed overflow respectively.

Summary

The ALU is the central combinational element of a CPU that implements arithmetic and logical micro-operations. Its design proceeds by building reliable arithmetic and logical blocks, and then combining them with selection circuitry and flag generation. Practical ALU design balances required functionality, performance (delay), silicon area, and power, while ensuring the control unit and registers supply operands and handle results correctly.