Data Transfer & Manipulation - Computer Architecture & Organisation (CAO)

Data Transfer and Manipulation

Data transfer and data manipulation form the basic instruction classes that enable a processor to move information and perform computations. Data transfer instructions cause the transfer of binary data from one location to another without changing the bit pattern. The most common data transfers are:

• Between memory and processor registers
• Between processor registers and input/output devices
• Between processor registers themselves

Data Transfer Instructions - Details and Examples

Data transfer instructions implement operations such as load, store, and move. These instructions differ by the source and destination addressing modes and by whether they access memory, registers or I/O. Important concepts and variants are:

• Load / Store model - separate instructions to read from memory into a register (load) and to write register contents to memory (store).
• Register-to-register moves - transfer data directly between registers; usually fast and used for temporary values and expression evaluation.
• Memory-to-memory transfers - some architectures allow direct memory-to-memory moves, but these are typically slower and less common in RISC designs.
• I/O transfers - performed either through memory-mapped I/O (device registers appear in the memory address space) or port-mapped I/O (special I/O address space); direct memory access (DMA) allows devices to transfer blocks of memory without continuous CPU intervention.
• Addressing modes - immediate, direct, indirect, register indirect, indexed, based, and base+offset affect how the effective address is computed for load/store instructions.
• Alignment and endianness - word alignment affects transfer performance; endianness (big-endian vs little-endian) defines byte order during multi-byte transfers.

Data Manipulation Instructions

Data manipulation instructions perform arithmetic, logical and bitwise operations on data. They provide the computational capability of a processor and typically affect condition codes or status flags used for subsequent decisions.

• Arithmetic operations - addition (ADD), subtraction (SUB), multiplication (MUL), division (DIV), increment, decrement.
• Logical operations - AND, OR, NOT, XOR (exclusive OR); used for bit masking, setting and clearing fields.
• Shift and rotate - logical shift left/right, arithmetic shift (preserve sign), rotate left/right; used for multiplication/division by powers of two and bit-field manipulation.
• Compare - perform a subtraction-like operation to set condition flags (zero, sign, carry, overflow) without storing the result; used by conditional branches.
• Sign/zero extension and truncation - convert between data widths (for example, from 8-bit to 32-bit)
• Floating-point operations - on architectures with floating-point units: floating add, subtract, multiply, divide, comparisons and conversions.
• Condition codes / status flags - results often set flags such as zero (Z), carry (C), negative/sign (N), and overflow (V) which influence program control instructions.

Program Control Instructions

Program control instructions alter the flow of instruction execution by changing the contents of the program counter (PC). Execution of such an instruction creates a break in the sequential execution of instructions. Typical program-control operations include:

• Unconditional transfer of control (jump, branch)
• Conditional branches that test condition codes or registers
• Subroutine call and return (procedure call and return)
• Interrupts, traps and exceptions that cause transfer to service routines

Subroutine call and Return

A subroutine call instruction consists of an operation code together with an address (or a means to compute the address) that specifies the beginning of the subroutine. A call is executed by performing two main tasks:

• The address of the next instruction (the return address) is stored in a temporary location (commonly the stack or a link register) so the subroutine knows where to return.
• Control is transferred to the beginning of the subroutine.

The last instruction of every subroutine, commonly called return from subroutine, transfers the return address from the temporary location into the program counter. This results in a transfer of program control back to the instruction following the original call.

• Stack-based calls: the caller pushes arguments and the return address on the stack; the callee allocates space for local variables by adjusting the stack pointer; on return the callee restores stack and returns using the saved return address.
• Link-register calls: some architectures (for example many RISC systems) place the return address in a dedicated register (link register) rather than on the stack; this can be faster for leaf routines.
• Activation record / stack frame: stores return address, saved registers, parameters, local variables, and sometimes control link or frame pointer to allow nested calls and recursion.
• Parameter passing: may use registers, stack, or a combination; calling conventions define which registers the caller must save and which the callee must preserve.

Interrupt

An interrupt transfers control to a predefined service routine (interrupt service routine, ISR) in response to an external or internal event. The interrupt procedure resembles a subroutine call but differs in important ways:

• The interrupt is usually initiated by an external or internal signal rather than by the execution of a normal instruction.
• The address of the interrupt service routine is determined by hardware (through an interrupt vector or table) rather than from the address field of an instruction.
• An interrupt procedure usually saves the complete CPU state (registers, program counter, processor status word) rather than storing only the program counter.

Typical stages in handling an interrupt are:

1. The processor recognises an interrupt request and finishes the current instruction (depending on architecture).
2. The processor acknowledges the interrupt request (if required) and may disable or mask further interrupts according to priority and nesting rules.
3. The processor saves the CPU state necessary to resume the interrupted program (program counter, status flags, and usually general-purpose registers).
4. The processor determines the source of the interrupt and locates the address of the appropriate ISR (vectored or via an interrupt controller).
5. The processor transfers control to the ISR and the ISR executes to service the event.
6. On completion, the ISR restores the saved CPU state and executes a return-from-interrupt instruction that restores the program counter and status so normal execution continues.

• Hardware vs software interrupts - hardware interrupts originate from peripherals or external signals; software interrupts (or traps) are generated by instructions to request OS services or to handle exceptional conditions.
• Vectored vs non-vectored - in vectored interrupts the hardware provides the address of the ISR; in non-vectored the CPU or interrupt controller must determine the service address.
• Priority and masking - multiple interrupts are prioritised; masking allows selective disabling of interrupts during critical regions.
• Context switching and nesting - careful saving/restoring of context is required for nested interrupts; OS and hardware cooperate to manage preemption and reentrancy.
• Latency - the time between an interrupt request and the start of the ISR is important for real-time systems; design choices (pipeline flushing, saving state, priorities) affect latency.

Summary and Design Considerations

Data transfer, data manipulation and program control instructions together define the capabilities and performance characteristics of a CPU. When designing or using an instruction set, consider:

• Instruction complexity: fewer, orthogonal instructions (RISC) vs more complex single instructions (CISC).
• Data movement cost: favour register operations and minimise slow memory accesses where possible.
• Calling conventions and stack discipline for reliable subroutine behaviour and efficient context switching.
• Interrupt handling policy to meet system responsiveness and correctness (masking, priorities, context save/restore).
• Clear documentation of addressing modes, side effects (flags), and exception behaviour to allow correct and optimised programming.