RISC & CISC - Computer Architecture & Organisation (CAO) - Computer Science

Table of Contents
1. RISC and CISC
2. Complex Instruction Set Computers (CISC)
3. Reduced Instruction Set Computers (RISC)
4. Comparison: RISC versus CISC
5. Overlapped register windows
6. Berkeley RISC I
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RISC and CISC

• An important aspect of computer design is the instruction set of the processor; the instruction set determines how machine-language programs are constructed and how programmers and compilers express algorithms for the machine.
• Early computers had simple and small instruction sets to minimise the required hardware.
• The advent of the integrated circuit (IC) made digital hardware cheaper, and instruction sets began to increase both in number and in complexity.
• Many later computers provided well over 100 instructions, supported a variety of data types, and offered many addressing modes.

Complex Instruction Set Computers (CISC)

• The move toward greater hardware complexity was driven by several aims: upgrading existing models to provide more applications for customers, adding instructions to simplify translation from high-level languages to machine code, and moving functions from software into hardware.
• A computer with a large number of complex instructions is classified as a Complex Instruction Set Computer (CISC).
• One motive for CISC designs was to simplify compilation and improve overall performance by providing single machine instructions that correspond closely to high-level language statements.
• Examples of CISC architectures include the DEC VAX, IBM System/370, and early Intel families such as 8085, 8086 and the 80x86 series.

Major characteristics of CISC architecture

• A large number of instructions, typically from about 100 to 250 instructions.
• Presence of specialized instructions that perform complex or infrequently used tasks.
• A large variety of addressing modes, typically from 5 to 20 different modes.
• Variable-length instruction formats, which complicate instruction decoding.
• Instructions that can directly manipulate operands in memory (memory-to-memory operations).
• Relatively slower performance when instructions cause many memory read/write operations.
• Extensive use of microprogramming-a special program stored in control memory used to implement instruction timing and sequencing (fetch, decode, execute, etc.).
• Major design complexity in microprogram development; control logic tends to be microprogrammed rather than hardwired.
• Typically fewer registers on-chip; designers often used a small set of general-purpose registers to keep costs down.

Reduced Instruction Set Computers (RISC)

A Reduced Instruction Set Computer (RISC) uses a smaller set of simple instructions so that individual instructions can be executed very quickly within the CPU, reducing the frequency of memory accesses for typical computations.

• The RISC concept attempts to reduce the execution cycle time by simplifying the instruction set and the implementation.
• RISC machines provide a small set of instructions, emphasising register-to-register operations and simple load/store instructions for memory access.
• Each operand is typically brought into a register using a load instruction, computations are performed on register contents, and results are written back to memory using store instructions.
• Simplifying the instruction set encourages compiler optimisation and efficient register manipulation.
• RISC instruction sets often include immediate operands and relative addressing modes for branches, but avoid many complex addressing modes.

Major characteristics of RISC architecture

• Relatively few instructions compared with CISC designs.
• Relatively few addressing modes.
• Memory access is limited to explicit load and store instructions; arithmetic and logical instructions operate on registers only.
• All computation operations are performed in the processor registers.
• Fixed-length, easily decoded instruction formats that simplify instruction fetch and decode stages.
• Design goal of single-cycle or few-cycle instruction execution for many instructions.
• Control implemented by hardwired logic rather than by microprogramming, reducing control-store overhead.

Other characteristics commonly attributed to RISC architecture

• A relatively large number of registers in the processor unit to reduce memory traffic.
• Use of overlapped register windows to speed up procedure call and return by avoiding frequent saving and restoring of registers.
• Efficient instruction pipelining so fetch, decode and execute phases overlap.
• Strong compiler support for translating high-level languages into efficient machine code that exploits registers and pipelining.
• Performance studies sometimes conflate the benefits of a reduced instruction set with the benefits of a large register file; both contribute to observed speed-ups.
• RISC processors often use less chip area for the core CPU; this allows extra functions (for example, memory management or floating-point units) to be included on the same chip or as separate chips more economically.
• Simpler RISC cores can be designed more quickly and may achieve 2 to 4 times the performance of comparable contemporary CISC designs in certain workloads, depending on implementation and compiler quality.

Comparison: RISC versus CISC

Overlapped register windows

• Some processors provide multiple register banks and allocate a separate bank (window) to each procedure; this eliminates the frequent need for saving and restoring register values to memory on procedure calls.
• Other architectures use the memory stack to store parameters and local variables; this requires memory accesses for each stack operation and can reduce performance.
• RISC processors sometimes use overlapped register windows so that parameters can be passed between procedures without memory traffic and without saving all registers on each call and return.
• Typical parameters used to describe a register-window organisation are:
  • Number of global registers = G
  • Number of local registers in each window = L
  • Number of registers common to two adjacent windows = C
  • Number of windows = W
• The number of registers available for each window is:

  Window size = L + 2C + G

• The total number of registers required in the processor is:

  Register file = (L + C)W + G

• A total of 74 registers (example organisation).
• Global registers = 10; these are common to all procedures.
• 64 registers are divided into 4 windows (A, B, C and D) in the example.
• Each register window contains 10 local registers in the example given.
• There are two sets of 16 registers that are common to adjacent procedures (shared overlap between windows).

Berkeley RISC I

• The Berkeley RISC I is a 32-bit integrated-circuit CPU design that embodies many RISC principles.
• It supports 32-bit addressing and 8-, 16- or 32-bit data accesses.
• It uses a 32-bit instruction format and implements a small instruction set of 31 instructions.
• There are three basic addressing modes: register addressing, immediate operand, and PC-relative addressing for branch instructions.
• It has a register organisation that implements a large register file with register windows: the design mentions a register file of 138 registers composed of 10 global registers and several windows (for example, 8 windows of 32 registers each in the description).
• The 32 registers in each window are organised with overlapping regions to implement fast procedure calls and parameter passing.

• The instruction formats used in Berkeley RISC I include formats for register-to-register instructions and memory-access instructions.
• Seven bits of the opcode specify the operation, and an eighth bit indicates whether to update the condition/status bits after an ALU operation.
• For register-to-register (three-address) instructions:
  • The 5-bit Rd field selects one of the 32 registers as the destination for the result.
  • The operation uses data specified in fields Rs and S2 (the second source may be either a register or an immediate value).
• For memory-access instructions:
  • Rs specifies a 32-bit base address in a register.
  • S2 specifies an offset (index) to form an effective address.
  • A register that always contains all zeros can be used in any field to denote a zero quantity (useful for certain immediate or addressing modes).
• A third instruction format combines certain fields to form a 19-bit relative address Y used primarily for jump and call instructions.
• For jump instructions the COND field replaces the Rd field and specifies one of 16 possible branch conditions.