Symbolic Microinstructions - Computer Architecture & Organisation (CAO)

Table of Contents
1. Symbolic Microinstructions
2. Sample Format
3. Fetch Subroutine
4. Binary Microprogram
5. Control Memory
6. Concluding Remarks and Practical Notes
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Symbolic Microinstructions

Symbolic microinstructions provide a readable, assembly-like notation for the microprogram that controls the datapath of a processor. The symbols defined in Table 3-1 (referenced here as an authoritative source) may be used to specify microinstructions in symbolic form. Symbols are used in microinstructions just as symbols are used in conventional assembly language: they name fields, microoperations and branch/control actions. The simplest way to define an assembly language for a microprogram is to give symbolic names for each field of a microinstruction and to allow the programmer to define symbolic addresses.

Sample Format

A typical symbolic microinstruction contains five fields in the following order: label, micro-ops, CD, BR, and AD. Each field has a restricted set of values and a specific syntactic form.

• Label: May be empty or may specify a symbolic address terminated with a colon (for example, LOOP:).
• Micro-operations: One, two or three symbols separated by commas; the symbol NOP is used when the microinstruction performs no microoperations.
• CD (Condition): One of the letters {U, I, S, Z} where:
  • U: Unconditional branch (no condition)
  • I: Indirect address bit
  • S: Sign of the accumulator (AC)
  • Z: Zero value in the accumulator (AC)
• BR (Branch type): One of the symbols {JMP, CALL, RET, MAP}.
• AD (Address field): Specifies the next value of the control address register; it may be a symbolic address, the keyword NEXT, or it may be left empty. When the BR field contains RET or MAP, the AD field is left empty.

Fetch Subroutine

The fetch subroutine is responsible for reading an instruction word from memory, decoding the instruction opcode, and updating the program counter (PC). In a typical microprogrammed control store layout described here, the organisation of control memory and the placement of the fetch routine are planned to simplify mapping from opcodes to the beginning of each instruction routine.

• The control storage contains 128 words, each a 20-bit microinstruction.
• The first 64 words are reserved for the microprogram routines of the 16 machine instructions; this allocation gives four control-memory words per machine instruction.
• The remaining 64 words are available for other purposes such as the fetch routine and shared subroutines.
• A convenient starting location for the fetch routine is address 64 in control memory.
• The fetch routine is typically composed of three microinstructions; these three microinstructions can be expressed in three equivalent representations:
  • register-transfer notation
  • symbolic microinstruction notation
  • binary microinstruction encoding

• The symbolic representation of the three fetch microinstructions is shown below the register-transfer form and before the binary form.

• The binary representation of those three fetch microinstructions is shown next.

• The execution of the third microinstruction in the fetch routine is a MAP operation that forms a branch address by inserting the four opcode bits into a fixed address pattern. The address pattern used is 0xxxx00 where xxxx are the four bits of the operation code. For example, the opcode for ADD is 0000, so the mapped start address for the ADD routine is the word whose address matches that bit pattern.
• Thus the first addresses for the 16 instruction routines are 0, 4, 8, 12, 16, 20, ..., 60 - i.e., the pattern 0xxxx00 with xxxx running from 0000 to 1111.
• Each instruction routine must provide microinstructions both for evaluating the effective address (if any) and for executing the operation.
• The indirect addressing mode is applicable to all memory-reference instructions; to avoid duplication, the microinstructions required for indirect addressing can be stored once as a subroutine.
• The indirect subroutine, named INDRCT here, is located immediately after the fetch routine in control memory so it can be shared by all routines that need it.

How mapping and the indirect subroutine work

• The MAP microinstruction causes a branch into the block of addresses reserved for instruction routines; specifically it selects the start address whose low bits are 00 and whose middle bits are the opcode bits.
• The first microinstruction in a machine-instruction routine tests the indirect bit I. If I = 1, the routine issues a CALL to the common indirect subroutine INDRCT.
• The return address for a CALL is stored in the subroutine register SBR, so that a subsequent RET returns control to the correct place.
• The INDRCT subroutine in this design consists of two microinstructions that access memory to obtain the effective address and then return:
  • INDRCT: READ U JMP NEXT
  • DRTAR: U RET
• Here, the first instruction of INDRCT performs a memory read to fetch the address stored at the operand location and then updates the appropriate register(s); the second microinstruction returns to the calling routine by executing RET.
• After address calculation (including any indirect handling), the execution microinstructions for, say, an ADD instruction typically perform:
  • read the operand from memory into the data register DR, and
  • perform the add between DR and the accumulator AC, then branch back to the fetch routine start.

Binary Microprogram

A symbolic microprogram must be translated into the binary encoding used by the control memory. This translation can be performed by an assembler program or, for small microprograms, by hand. The binary list produced is the exact sequence of 20-bit words to be stored in control memory.

• An equivalent binary form of the symbolic microprogram is provided in the cited Table 7-3 (this table contains the binary encoding for each symbolic microinstruction in the example).
• Every control-memory word must have some binary value; even addresses that are not used in the microprogram (for example address 3 in the example) must be filled with a defined bit pattern such as all zeros.
• As a safety measure, it is prudent for unused or reserved locations to contain a microinstruction that branches to a safe routine (for example, jump to address 64, the fetch routine), so that if the control address register (CAR) is corrupted (e.g. by noise) the machine will recover to a known state.

Control Memory

The control memory (control store) may be implemented as ROM or RAM; each implementation has advantages and limitations that affect system cost, flexibility and performance.

• When a ROM is used for the control memory, the binary microprogram list serves as the truth table for fabricating the ROM mask. To modify the instruction set or change the microprogram, a new binary microprogram must be produced and a new ROM must be manufactured (masked) from that truth table.
• When a RAM is used for the control memory, the microprogram can be altered simply by writing a new pattern of 1's and 0's into control memory; this permits easier updates, experimentation and dynamic modification of the control microcode.
• Despite the flexibility of RAM, many microprogram systems employ ROM because it is usually cheaper and faster than RAM for fixed microprograms.

Concluding Remarks and Practical Notes

• Symbolic microinstructions improve readability and reduce errors when developing microcode; they must, however, be correctly assembled into the binary encoding expected by the control store.
• Careful organisation of control memory (for example reserving a block for instruction routines and locating shared subroutines such as INDRCT nearby) reduces duplication and conserves control-store space.
• Always provide safe default microinstructions for unused control-store locations to reduce the risk from accidental corruption of the control address register.
• Keep symbolic field conventions consistent: use the specified condition codes {U, I, S, Z}, branch types {JMP, CALL, RET, MAP}, and standard microoperation names (READ, NOP, etc.) so that assemblers and engineers can interoperate reliably.