Pipeline Hazards | Computer Architecture & Organisation (CAO) - Computer Science Engineering (CSE) PDF Download

Pipeline Hazards
A pipeline hazard occurs when the pipeline, or some portion of the pipeline, must stall because conditions do not permit continued execution. Such a pipeline stall is also referred to as a pipeline bubble. There are three types of hazards: resource, data, and control.

Resources Hazards 
A resource hazard occurs when two (or more) instructions that are already in the pipeline need the same resource. The result is that the instructions must be executed in serial rather than parallel for a portion of the pipeline. A resource hazard is sometime referred to as a structural hazard.

Let us consider a simple example of a resource hazard.Assume a simplified five-stage pipeline, in which each stage takes one clock cycle. In Figure 3.6a which a new instruction enters the pipeline each clock cycle. Now assume that main memory has a single port and that all instruction fetches and data reads and writes must be performed one at a time. In this case, an operand read to or write from memory cannot be performed in parallel with an instruction fetch. This is illustrated in Figure 3.6b, which assumes that the source operand for instruction I1 is in memory, rather than a register. Therefore, the fetch instruction stage of the pipeline must idle for one cycle before beginning the instruction fetch for instruction I3. The figure assumes that all other operands are in registers

Pipeline Hazards | Computer Architecture & Organisation (CAO) - Computer Science Engineering (CSE)

Data Hazards 
A data hazard occurs when two instructions in a program are to be executed in sequence and both access a particular memory or register operand. If the two instructions are executed in strict sequence, no problem occurs but if the instructions are executed in a pipeline, then the operand value is to be updated in such a way as to produce a different result than would occur only with strict sequential execution of instructions. The program produces an incorrect result because of the use of pipelining.

As an example, consider the following x86 machine instruction sequence: 

ADD EAX, EBX /* EAX = EAX + EBX
SUB ECX, EAX /* ECX = ECX - EAX

The first instruction adds the contents of the 32-bit registers EAX and EBX and stores the result in EAX. The second instruction subtracts the contents of EAX from ECX and stores the result in ECX. 

Figure 3.7 shows the pipeline behaviour. The ADD instruction does not update register EAX until the end of stage 5, which occurs at clock cycle 5. But the SUB instruction needs that value at the beginning of its stage 2, which occurs at clock cycle 4. To maintain correct operation, the pipeline must stall for two clocks cycles. Thus, in the absence of special hardware and specific avoidance algorithms, such a data hazard results in inefficient pipeline usage. There are three types of data hazards;

Pipeline Hazards | Computer Architecture & Organisation (CAO) - Computer Science Engineering (CSE)

Read after write (RAW), or true dependency:.A hazard occurs if the read takes place before the write operation is complete.

Write after read (RAW), or antidependency: A hazard occurs if the write operation completes before the read operation takes place.

Write after write (RAW), or output dependency: Two instructions both write to the same location. A hazard occurs if the write operations take place in the reverse order of the intended sequence. The example of Figure 3.7 is a RAW hazard.

Control Hazards 
 A control hazard, also known as a branch hazard, occurs when the pipeline makes the wrong decision on a branch prediction and therefore brings instructions into the pipeline that must subsequently be discarded.

The document Pipeline Hazards | Computer Architecture & Organisation (CAO) - Computer Science Engineering (CSE) is a part of the Computer Science Engineering (CSE) Course Computer Architecture & Organisation (CAO).
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FAQs on Pipeline Hazards - Computer Architecture & Organisation (CAO) - Computer Science Engineering (CSE)

1. What are pipeline hazards in computer architecture?
Ans. Pipeline hazards in computer architecture refer to situations where the instruction pipeline is stalled or delayed, leading to a decrease in performance. These hazards can occur due to various reasons such as data dependencies, control dependencies, and structural hazards.
2. What is a data hazard in pipeline processing?
Ans. A data hazard is a type of pipeline hazard that occurs when an instruction depends on the result of a previous instruction that is still being processed. This dependency causes a stall in the pipeline, as the subsequent instruction needs to wait for the data to be available before it can proceed.
3. How can data hazards be resolved in pipeline processing?
Ans. Data hazards can be resolved in pipeline processing using techniques such as forwarding or bypassing. Forwarding involves directly passing the required data from one stage of the pipeline to another, bypassing the need to wait for it to be written back to the register file. This helps in reducing stalls and improving pipeline performance.
4. What is a control hazard in pipeline processing?
Ans. A control hazard is a type of pipeline hazard that occurs when the pipeline needs to make a decision based on the outcome of a branch instruction. Since the outcome is determined in a later stage of the pipeline, it may cause incorrect instructions to be fetched and executed. This leads to a pipeline stall or a need for flushing and restarting the pipeline.
5. How can control hazards be mitigated in pipeline processing?
Ans. Control hazards can be mitigated in pipeline processing through techniques such as branch prediction and branch target prediction. Branch prediction involves predicting the outcome of a branch instruction before it is determined, allowing the pipeline to continue fetching and executing instructions based on the prediction. Branch target prediction helps in predicting the target address of a branch instruction, reducing the delay caused by fetching the target instruction. These techniques help in reducing the impact of control hazards on pipeline performance.
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