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Electrical Engineering (EE) Exam  >  Electrical Engineering (EE) Tests  >  Test: Inverter Delays - Electrical Engineering (EE) MCQ

Test: Inverter Delays - Electrical Engineering (EE) MCQ


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10 Questions MCQ Test - Test: Inverter Delays

Test: Inverter Delays for Electrical Engineering (EE) 2024 is part of Electrical Engineering (EE) preparation. The Test: Inverter Delays questions and answers have been prepared according to the Electrical Engineering (EE) exam syllabus.The Test: Inverter Delays MCQs are made for Electrical Engineering (EE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Inverter Delays below.
Solutions of Test: Inverter Delays questions in English are available as part of our course for Electrical Engineering (EE) & Test: Inverter Delays solutions in Hindi for Electrical Engineering (EE) course. Download more important topics, notes, lectures and mock test series for Electrical Engineering (EE) Exam by signing up for free. Attempt Test: Inverter Delays | 10 questions in 10 minutes | Mock test for Electrical Engineering (EE) preparation | Free important questions MCQ to study for Electrical Engineering (EE) Exam | Download free PDF with solutions
Test: Inverter Delays - Question 1
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The resistance value associated with Rp.u is

Detailed Solution for Test: Inverter Delays - Question 1

 The resistance value associated with Rp.u. is 4Rs. Resistance is the measure of difficulty to pass an electric current through that material.

Test: Inverter Delays - Question 2
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The resistance value associated with Rp.d. is

Detailed Solution for Test: Inverter Delays - Question 2

The resistance value associated with Rp.d. is 1Rs. This is the measure of difficulty to pass current through the pull-down device.

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Test: Inverter Delays - Question 3
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The overall delay of nMOS inverter pair is

Detailed Solution for Test: Inverter Delays - Question 3

 The overall delay of nMOS inverter pair is Ʈ+4Ʈ = 5Ʈ. This delay is the time taken for the input signal to get inverted and arrive at the output.

Test: Inverter Delays - Question 4
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 The inverter pair delay for inverters having 4:1 ratio is
Detailed Solution for Test: Inverter Delays - Question 4

The inverter pair delay for inverters having 4:1 ratio is 5Ʈ. This measure of delay is for two inverters, in which the output of the first is given as the input for the second inverter.

Test: Inverter Delays - Question 5
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The assymetry of resistance value can be eliminated by
Detailed Solution for Test: Inverter Delays - Question 5

The assymetry of resistance value can be eliminated by increasing the width of the p-device channel.

Test: Inverter Delays - Question 6
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The ratio of rise time to fall time can be equated to
Detailed Solution for Test: Inverter Delays - Question 6

The ratio of rise time to fall time can be equated to βn/βp. Rise time is the time taken by a signal to change from a specified low value to a specified high value. Fall time is the time taken for the amplitude of a pulse to decrease from a specified value to another specified value.

Test: Inverter Delays - Question 7
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The value µn is equal to
Detailed Solution for Test: Inverter Delays - Question 7

The value of µn = 2.5 µp. This shows that µn value is greater than that of the µp.

Test: Inverter Delays - Question 8
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Which quantity is slower?
Detailed Solution for Test: Inverter Delays - Question 8

Rise time is slower by a factor of 2.5 than fall time.

Test: Inverter Delays - Question 9
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 Condition for achieving symmetrical operation is
Detailed Solution for Test: Inverter Delays - Question 9

The condition for achieving symmetrical operation is Wp = 2.5 Wn.

Test: Inverter Delays - Question 10
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 Rise time and fall time is _____ to load capacitance CL
Detailed Solution for Test: Inverter Delays - Question 10

 Rise time and fall time is directly proportional to load capacitance CL.

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