Test: MOS Circuits Area Capacitance And Delay Unit - Electrical Engineering (EE) MCQ

Inter electrode capacitance

Stray capacitance

Junction Parasitic capacitance

All of the mentioned

Source diffusion regions

Gate diffusion regions

Drain diffusion region

All of the mentioned

Concentration of the impurity doped

Size of the total drain diffusion area

Charges stored in the capacitor

None of the mentioned

Drain diffusion capacitance

Gate oxide capacitance

Interconnect capacitance

Junction parasitic capacitance

Gate diffusion capacitance

Gate parasitic capacitance

Gate oxide capacitance

All of the mentioned

Drain capacitance in series with input capacitance

Drain capacitance + interconnect capacitance +input capacitance

Drain capacitance + interconnect capacitance – input capacitance

Drain capacitance in parallel with input capacitance

Area between the interconnect lines

Interconnect lines between the gates

Inter electrode capacitance of interconnect lines

None of the mentioned

Charges present on the gate

Polarity of the gate

Charges present on the substrate

Area of the gate

5

2

1

10

:a) (√10).Cj.xj

(√5).Cj.xj

(√10).Cj.xj²

(√10).Cj.xj³

1

0.4

0.2

4

Parasitic capacitance

Interconnect capacitance

Junction capacitance

Diffusion capacitance

1.75

4

8

16

0.01pF

0.0032pF

0.0023pF

All of the mentioned

Capacitance of gate to channel of MOS transistor having W = L dimensions

Capacitance of gate to channel of n-MOS transistor having W = 3L dimensions

Capacitance of gate to channel of p-MOS transistor having 3W = L dimensions

Capacitance of gate to channel of n-MOS transistor having W = L dimensions and p-MOS having W=3L dimensions