Test: Design Of ALU Subsystem - Electrical Engineering (EE) MCQ

Design is largely a matter of topology of communication rather than the detailed logic circuit design.

Regularity is a qualitatie parameter and it should be high as possible to minimize the design effort required for any system.

Regularity is the ratio of total transistors in the chip to total transistors that must be designed in detail.

Good design system must have regularity in the range of 50 to 100 or more and regular structures such as memories achieve very high figures.

The sum is stored in parallel at the output of the adder from where it may be fed through the shifter and back to the register array.

 The shifter is unclocked but must be connected to 4 shift control lines. Carry out and Carry in signal must also be connected.

 If the two bit number is 1 1 and the previous carry is 0 the sum is 0 and carry is 1. This can be obtained by first adding the two numbers 1 and 1. Sum will be 0 and carry is 1. Later add the previous carry 0 to it. Now the sum is finally 0 and final carry will be 1.

 In n-bit adder, n adder elements must be cascaded with carry out connecting to carry in. This carry chain will have more pass transistors connected in series which will give slow response. Thus suitable buffer can be used in between.

 In adders, the previous carry signal can also be given using propogate signal pk which is ex-or of two bits ak and bk and also using generate signal gk which is ‘and’ of ak and bk.

Using BiCMOS technology, speed improvement can be obtained by a factor of two over CMOS technology. This arrangement works will lower input voltage swings to achieve higher speed.