31 Year NEET Previous Year Questions: Semiconductor Electronics - 3 - NEET MCQ

The given truth table is of
(OR gate + NOT gate) ≡ NOR gate

In reverse bias, the current through a p-n
junction is almost zero.

(a) is a NAND gate so output is 

(b) is a NOR gate so output is  

(c) is a NAND gate so output is 

(d) is a XOR gate so output is 

Following is NAND Gate

Relation between A, B and C shows that

During the formation of a junction diode,
holes from p-region diffuse into n-region and
electrons from n-region diffuse into p-region.
In both cases, when an electron meets a hole,
they cancel the effect of each other and as a
result, a thin layer at the junction becomes
free from any of charge carriers. This is called
depletion layer. There is a potential gradient
in the depletion layer, negative on the p-side
and positive on the n-side. The potential
difference thus developed across the
junction is called potential barrier.

We know that in forward bias of p-n junction
diode, when positive terminal is connected
to p-type diode, the repulsion of holes takes
place which decreases the width of potential
barrier by striking the combination of holes
and electrons.

Depletion layer is formed by diffusion of
holes and electrons from p-type
semiconductor to n-type semiconductor and
vice-versa. Hence, donor and acceptor atom
get positive and negative charge leading to
formation of p-n junction. Thus, donor and
acceptor are immobile.

n-type of silicon semiconductor is formed
when impurity is mixed with pentavalent
atom. Out of given choices only phosphorus
is pentavalent.

Holes are produced due to missing of
electrons.

P, Q and R are related as R = P. Q which is
relation of AND gate.

As we know that I_e = I_c = I_b
Divide both side by I_e

As A is at higher potential than B, hence
current will flow from A to B i.e. from p
junction to n junction and diode is forward
biased.

Which is truth table of NAND gate

At 0K, motion of free electrons stop. Hence
conductivity becomes zero. Therefore, at 0K
intrinsic semiconductor becomes insulator.

We have, 

Light is trasmitted through optical fibre due
to multiple total internal reflections.

In forward biasing, the diode conducts. for ideal junction diode, the forward resistance is zero; therefore, entire applied voltage occurs across external resistance R i.e. there occurs no potential drop, so potential across R is V in forward biased.

2: The n-side is at a higher electrical potential than the p-side.

In a p-n junction, a p-type semiconductor material is joined to an n-type semiconductor material. This creates a region called the depletion region, which is a region where the concentration of charge carriers (electrons and holes) is significantly lower than in the surrounding materials.

In equilibrium, the electrical potential of the p-side is lower than that of the n-side, due to the difference in the concentration of charge carriers. The electrical potential of the p-side is attracted to the higher concentration of holes on the p-side, while the electrical potential of the n-side is attracted to the higher concentration of electrons on the n-side. This creates an electrical potential difference across the p-n junction, with the n-side at a higher potential than the p-side.

Option 1 is incorrect because the potential of the p and n-sides does not alternate. Option 3 is incorrect because the p-side is at a lower potential than the n-side. Option 4 is incorrect because the p and n-sides are at different potentials. Therefore, the correct answer is 2: The n-side is at a higher electrical potential than the p-side.

In case of full wave rectifier,
Fundamental frequency = 2 × mains
frequency
= 2 × 50 = 100Hz.

When the collector is positive and emitter is
negative w.r.t. base, it causes the forward
biasing for each junction, which causes
conduction of current.

Barrier potential does not depend on diode
design while barrier potential depends upon
temperature, doping density, and forward
biasing.

Y = A. B by Demorgan therorem
∴ This diagram performs the function of
AND gate.

Output of upper AND gate = 

Output of lower AND gate = 

∴ Output of OR gate, Y = 

This is Boolean expression for XOR gate.