Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  Test: Pipelining- 1 - Computer Science Engineering (CSE) MCQ

Test: Pipelining- 1 - Computer Science Engineering (CSE) MCQ


Test Description

10 Questions MCQ Test - Test: Pipelining- 1

Test: Pipelining- 1 for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Test: Pipelining- 1 questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Pipelining- 1 MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Pipelining- 1 below.
Solutions of Test: Pipelining- 1 questions in English are available as part of our course for Computer Science Engineering (CSE) & Test: Pipelining- 1 solutions in Hindi for Computer Science Engineering (CSE) course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: Pipelining- 1 | 10 questions in 30 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
Test: Pipelining- 1 - Question 1

Pipelining improves CPU performance due to

Detailed Solution for Test: Pipelining- 1 - Question 1

In pipelining, a number of functional units are employed in sequence to perform a single computation.

Test: Pipelining- 1 - Question 2

An instruction cycle refers to

Detailed Solution for Test: Pipelining- 1 - Question 2

An instruction cycle is the basic operational process of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction dictates and carries out those actions. Also called as fetch, decode-execute cycle.

1 Crore+ students have signed up on EduRev. Have you? Download the App
Test: Pipelining- 1 - Question 3

Given a 5 stage pipeline with stages taking 1,2, 3, 1, 1 units of time, the clock period of the pipeline is

Detailed Solution for Test: Pipelining- 1 - Question 3

Clock period of pipeline = Maximum delay of stages
= Max ( 1, 2, 3, 1, 1) = 3

Test: Pipelining- 1 - Question 4

Which of following registers processor used for fetch and execute operations?
1. Program counter
2. Instruction register
3. Address register

Detailed Solution for Test: Pipelining- 1 - Question 4

μ-instruction for fetch cycle:

So, PC, IR and address register are used.

Test: Pipelining- 1 - Question 5

A ________ is required to translate such microprogram into executable programs that can be stored in the control memory in microprogramming.

Detailed Solution for Test: Pipelining- 1 - Question 5

It is the definition of microassembler.

Test: Pipelining- 1 - Question 6

Which of the following statements is false about CISC architectures?

Detailed Solution for Test: Pipelining- 1 - Question 6

In RISC instruction set all arithmetic/logic instructions must be register-based but not in CISC.

Test: Pipelining- 1 - Question 7

The register which holds the address of the location to or from which data are to be transferred is known as

Detailed Solution for Test: Pipelining- 1 - Question 7

MAR is a register that holds the address of location to or from which data are to be transferred.

Test: Pipelining- 1 - Question 8

Consider a case where 4-segment pipeline with a clock cycle time 20 ns in each sub operation to execute 100 tasks. Assume that a non pipeline unit that can perform the same operation. Pipelined system will take how much time to complete the task?

Detailed Solution for Test: Pipelining- 1 - Question 8

For pipeline with K segment and n instruction
Time (pipeline ) = ( K + n - i ) tP
= ( 4 + 100 - 1 ) x 20 nsec
= (4 + 99) x 20 nsec 
= (103) x 20 nsec = 2060 nsec 

Test: Pipelining- 1 - Question 9

Find out the speed-up ratio between pipelined and non-pipelined system?

Detailed Solution for Test: Pipelining- 1 - Question 9

The needed for non pipelined processor

Speedup = 8000/2060 = 3.88

Test: Pipelining- 1 - Question 10

Assume that the time required for the eight functional units, which operate in each of the eight cycles, are as follows 5 ns, 8 ns, 6 ns, 10 ns, 15 ns, 12 ns, 6 ns, 8 ns. Assume that pipe lining adds 1 ns of overhead. Find the speedup versus the single cycle data path.

Detailed Solution for Test: Pipelining- 1 - Question 10

Since the unpipelined machine executes all instructions in a single clock cycle, its average time per instruction is simply clock time. The dock is equal to the sum of the times for each step in the execution.
∴ Average instructions execution time
= 5 + 8 + 6 + 1 0 + 15 + 12 + 6 + 8 
= 70
The dock cycle time on the pipelined machine must be the largest time for any stage in the pipeline (15 ns) + the overhead of 1 ns for a total of 16 ns.
∴ Speed from pipelining

Information about Test: Pipelining- 1 Page
In this test you can find the Exam questions for Test: Pipelining- 1 solved & explained in the simplest way possible. Besides giving Questions and answers for Test: Pipelining- 1, EduRev gives you an ample number of Online tests for practice

Top Courses for Computer Science Engineering (CSE)

Download as PDF

Top Courses for Computer Science Engineering (CSE)