GATE Computer Science Engineering(CSE) 2027 Test: Secondary Memory & DMA-

During DMA transfer, DMA controller takes over the busses to manage the transfer directly from I/O devices to memory or vice-versa.

Programmed I/O data transfer mode takes relatively more time than DMA and interrupt initiated I/O.

The CPU initializes the DMA by sending:
The starting address of the memory blocks where data are available (for read) or where data are to be stored. (For write)
The word count, which is the number of words in the memory.
Control to specify the mode of transfer such as read or write.

Assembler directives neither represents machine instructions to be included in the object program nor indicate the allocation of storage for constants or program variables.
Instead, these statements direct the assembler to take certain actions during the process of assembling a program. They are used to indicate certain things regarding how assembly of the input program is to be performed.

Daisy chained arbitration scheme requires 3 lines irrespective of the number of devices, A pair of REQ/GRANT lines are required in the case of independent request type arbitration and so for N devices 2N lines

For communication between can:
1. Contain one common bus for memory and I/O with common control lines.
2. Contain two separate buses, one for memory and other for I/O.
3. Contain one common bus for memory and I/O but have separate control line for each.

Data communication processor is the processor that communicate with remote terminals over telephone and other communication media in a serial fashion.