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Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Test  >  GATE Computer Science Engineering(CSE) 2027 Mock Test Series  >  Test: Combinational Circuit- 2 - Computer Science Engineering (CSE) MCQ

GATE Computer Science Engineering(CSE) 2027 Test: Combinational Circuit-


MCQ Practice Test & Solutions: Test: Combinational Circuit- 2 (15 Questions)

You can prepare effectively for Computer Science Engineering (CSE) GATE Computer Science Engineering(CSE) 2027 Mock Test Series with this dedicated MCQ Practice Test (available with solutions) on the important topic of "Test: Combinational Circuit- 2". These 15 questions have been designed by the experts with the latest curriculum of Computer Science Engineering (CSE) 2026, to help you master the concept.

Test Highlights:

  • - Format: Multiple Choice Questions (MCQ)
  • - Duration: 45 minutes
  • - Number of Questions: 15

Sign up on EduRev for free to attempt this test and track your preparation progress.

Test: Combinational Circuit- 2 - Question 1
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The following circuit

Can be represented as:

Detailed Solution: Question 1

From the given diagram we can see that

Test: Combinational Circuit- 2 - Question 2
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The circuit shown below converts.

Detailed Solution: Question 2

if input is 1010 it generate 1101 which is same as gray to binary code converter.

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Test: Combinational Circuit- 2 - Question 3
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The output of the circuit shown in following figure is equal to

Detailed Solution: Question 3

  • Analyze the circuit step by step:
    • Input A̅ and B: Pass through an AND gate to produce A̅B.
    • Input A and B̅: Pass through an AND gate to produce AB̅.
    • Combine A̅B and AB̅ using an OR gate to give A̅B + AB̅.
  • A̅B + AB̅ is the Boolean expression for the XOR gate.
  • The circuit output simplifies to A⊕B.
  • Correct answer: (a) A̅B + AB̅.

Test: Combinational Circuit- 2 - Question 4
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The circuit given in figure is to be used to implement the function   What is the values should be selected I and J?

Detailed Solution: Question 4


Test: Combinational Circuit- 2 - Question 5
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Minimum number of NAND gates required to implement sum in half-adder circuit is:

Test: Combinational Circuit- 2 - Question 6
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The following circuit is an implemented of:

1. Sum of full adder
2. Carry of half adder
3. Difference of full subtracte

Detailed Solution: Question 6

From the given circuit


For which only 1 and 3 satisfy. Hence correct option is (d),

Test: Combinational Circuit- 2 - Question 7
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The circuit below represents function X{A, B, C, D) as:

Detailed Solution: Question 7

The given circuit represents the implementation of four variable function using 8: 1 MUX here. D as taken as the fourth i/p and A, B, C act as select lines.

Test: Combinational Circuit- 2 - Question 8
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If half adders and full adders are implemented using gates, then for the addition of two 17 bit numbers (using minimum gates) the number of half adders and full adders required will be 

Detailed Solution: Question 8

As we know that n bit full adder circuit can represent (n + 1) bits sum. In order to represent addition of two 17 bits numbers we require minimum of 16 full adder and 1 half adder.
Note: For the first bit we can use either HA or FA. Hence, for addition of two 17 bit numbers inspire of 17 full adders we can perform the same task using 16 FA and 1 HA.
Hence (c) is the correct option.

Test: Combinational Circuit- 2 - Question 9
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To realize following function 'f'

How many minimum number of 2 input NAND gates are required

Detailed Solution: Question 9


So it required 10 NAND gates.

Test: Combinational Circuit- 2 - Question 10
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Minimum number of 2 x 1 multiplexers required to realize the following function,  Assume that inputs are available only in true forr and Boolean constants.1 and 0 are available.

Detailed Solution: Question 10

Test: Combinational Circuit- 2 - Question 11
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The number of full and half-adder required to add 16-bit numbers is

Detailed Solution: Question 11

To 16 bits number, 1 half and 15 full address or 16 full address are required.

Test: Combinational Circuit- 2 - Question 12
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 How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates?

Detailed Solution: Question 12

Test: Combinational Circuit- 2 - Question 13
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The following circuit implements a two-input AND gate using two 2-1 multiplexers.

What are the values of X1 X2, X3?

Detailed Solution: Question 13


Test: Combinational Circuit- 2 - Question 14
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Consider excess-3 code that is used to represent integers 0 through 9 as shown below:

Which of the following expressions is the correct one for an invalid code?

Detailed Solution: Question 14

Invalid code words are 0, 4, 4, 8, 11, 5.

So code will be a'c'd' + b'c'd' + bed + acd.

Test: Combinational Circuit- 2 - Question 15
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What logic function is performed by the circuit shown below:

Detailed Solution: Question 15


Hence the given circuit represents Half adder.

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About this Computer Science Engineering (CSE) Practice Test

This test contains 15 MCQs on Combinational Circuit- 2 with detailed solutions for each question. It is part of the GATE Computer Science Engineering(CSE) 2027 Mock Test Series course on EduRev, designed to align with the current Computer Science Engineering (CSE) syllabus. Each solution explains not just the correct answer but also gives you an understanding of the topic — not just to attempt the question but also help you prepare for the exam with practice.

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