Test: Sequential Circuits- 2

Question 1

If the initial state Q_A Q_B Q_C = 110, after how many clocks it get back same value

Accepted Answer

2

Answer

6

Answer

7

Answer

8

Question 2

What will be the current state after two clock pulses further from the number of pulses obtained from the above question?

Accepted Answer

110

Answer

011

Answer

100

Answer

101

Question 3

The divide by N counter as shown in figure. If initially Q₀ = 0, Q₁ = 1, Q₂ = 0. What is the value of N?

Accepted Answer

5

Answer

6

Answer

3

Answer

4

Question 4

Consider the circuit given below with initial state Q₀ = 1; Q₁ = Q₂ = 0. The state of the circuit is given by the value 4Q₂ + 2Q₁ + Q₀

Which one of the following is the. correct state sequence of the circuit?

Accepted Answer

1,2,5,3,7,6,4

Answer

1,3,4,6,7,5,2

Answer

1,2,7,3,5,6,4

Answer

1,6,5,7,2,3,4

Question 5

The following diagram represents a finite state machine which takes as input a binary number from the least significant bit

Which one of the following is TRUE?

Accepted Answer

It computes 2's complement of the input number.

Answer

It computes 1’s complement of the input number.

Answer

It increments the input number.

Answer

It decrements the input number.

Question 6

Consider the following circuit

The flip-flops are positive edge triggered DFFs. Each state is designated as a two bit string Q₀Q₁ Let the initial state be 00. The state transition sequence is:

Accepted Answer

Answer

Answer

Answer

Question 7

The functional difference between SR flip-flop and JK flip-flop is that JK flip-flop

Accepted Answer

Accepts both inputs 1

Answer

Is faster than SR flip-flop

Answer

Has a feed back path

Answer

Does not require external clock

Question 8

The number of flip-flops required in a modulo N counter is

Accepted Answer

Answer

Answer

Answer

Question 9

Consider the figure given below:

Initially all flip-flops are cleared. How many dock pulse have to be applied to the system before the output from FF3 becomes a HIGH level?

Accepted Answer

4

Answer

2

Answer

6

Answer

8

Question 10

The logic circuit shown below is a 3-bit

Accepted Answer

Synchronous binary up counter

Answer

Shift register

Answer

Asychronous binary up-counter

Answer

Asynchronous binary down-counter

Question 11

The inputs of the J-K flip-flop, shown below are:
PRESET = CLEAR = 1; J = K = 0
If a single clock pulse is applied the device will

Accepted Answer

Not change states

Answer

Toggle

Answer

Set

Answer

Reset

Question 12

Consider the following control circuit which contains a 3-bit register and a black box with some combinational logic

The initial state of the circuit is Q₁ Q₂ Q₃ = 000.
The circuit generates the control sequence.
(010) → ( 110) → ( 001) →(001) → . . . → ( 001)
On successive clock cycles. Which of the following sets of equations are implemented by the combinational logic in the black box?

Accepted Answer

Answer

Answer

Answer

Question 13

‘n’ flip-flop will divide the clock frequency by a factor of

Accepted Answer

2n

Answer

n2

Answer

n

Answer

log(n)

Question 14

Let a_n a_n-1 ... a₁ a₀ be the binary representation of an integer b. The integer b is divisible by 3 if

Accepted Answer

The difference of alternate sum, i.e., (a₀,+a₂+...) - a₁+a₃+...) is divided by 3

Answer

The number of one’s is divisible by 3

Answer

The number of one’s divisible by 3, but bot by 9

Answer

The number of zeroes is divisible 3

Question 15

If a clock with time period 'T' is used with n stage shift register, the output of final stage will be delayed by

Accepted Answer

(n -1)Tsec

Answer

nTsec

Answer

n/Tsec

Answer

(2n-1)Tsec

GATE Computer Science Engineering(CSE) 2027 Test: Sequential Circuits-

MCQ Practice Test & Solutions: Test: Sequential Circuits- 2 (15 Questions)

If the initial state Q_A Q_B Q_C = 110, after how many clocks it get back same value

What will be the current state after two clock pulses further from the number of pulses obtained from the above question?

The divide by N counter as shown in figure. If initially Q₀ = 0, Q₁ = 1, Q₂ = 0. What is the value of N?

Consider the circuit given below with initial state Q₀ = 1; Q₁ = Q₂ = 0. The state of the circuit is given by the value 4Q₂ + 2Q₁ + Q₀

Which one of the following is the. correct state sequence of the circuit?

The following diagram represents a finite state machine which takes as input a binary number from the least significant bit

Which one of the following is TRUE?

Consider the following circuit

The flip-flops are positive edge triggered DFFs. Each state is designated as a two bit string Q₀Q₁ Let the initial state be 00. The state transition sequence is:

The functional difference between SR flip-flop and JK flip-flop is that JK flip-flop

The number of flip-flops required in a modulo N counter is

Consider the figure given below:

Initially all flip-flops are cleared. How many dock pulse have to be applied to the system before the output from FF3 becomes a HIGH level?

The logic circuit shown below is a 3-bit

The inputs of the J-K flip-flop, shown below are:
PRESET = CLEAR = 1; J = K = 0
If a single clock pulse is applied the device will

‘n’ flip-flop will divide the clock frequency by a factor of

Let a_n a_n-1 ... a₁ a₀ be the binary representation of an integer b. The integer b is divisible by 3 if

If a clock with time period 'T' is used with n stage shift register, the output of final stage will be delayed by

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GATE Computer Science Engineering(CSE) 2027 Mock Test Series

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GATE Computer Science Engineering(CSE) 2027 Test: Sequential Circuits-

MCQ Practice Test & Solutions: Test: Sequential Circuits- 2 (15 Questions)

If the initial state QA QB QC = 110, after how many clocks it get back same value

What will be the current state after two clock pulses further from the number of pulses obtained from the above question?

The divide by N counter as shown in figure. If initially Q0 = 0, Q1 = 1, Q2 = 0. What is the value of N?

​Consider the circuit given below with initial state Q0 = 1; Q1 = Q2 = 0. The state of the circuit is given by the value 4Q2 + 2Q1 + Q0 Which one of the following is the. correct state sequence of the circuit?

The following diagram represents a finite state machine which takes as input a binary number from the least significant bit Which one of the following is TRUE?

Consider the following circuit The flip-flops are positive edge triggered DFFs. Each state is designated as a two bit string Q0Q1 Let the initial state be 00. The state transition sequence is:

The functional difference between SR flip-flop and JK flip-flop is that JK flip-flop

The number of flip-flops required in a modulo N counter is

Consider the figure given below: ​Initially all flip-flops are cleared. How many dock pulse have to be applied to the system before the output from FF3 becomes a HIGH level?

​The logic circuit shown below is a 3-bit

The inputs of the J-K flip-flop, shown below are: PRESET = CLEAR = 1; J = K = 0 If a single clock pulse is applied the device will

‘n’ flip-flop will divide the clock frequency by a factor of

Let an an-1 ... a1 a0 be the binary representation of an integer b. The integer b is divisible by 3 if

If a clock with time period 'T' is used with n stage shift register, the output of final stage will be delayed by

GATE Computer Science Engineering(CSE) 2027 Mock Test Series

GATE Computer Science Engineering(CSE) 2027 Mock Test Series

Top Courses for Computer Science Engineering (CSE)

About this Computer Science Engineering (CSE) Practice Test

Explore more Computer Science Engineering (CSE) Study Resources

If the initial state Q_A Q_B Q_C = 110, after how many clocks it get back same value

The divide by N counter as shown in figure. If initially Q₀ = 0, Q₁ = 1, Q₂ = 0. What is the value of N?

Consider the circuit given below with initial state Q₀ = 1; Q₁ = Q₂ = 0. The state of the circuit is given by the value 4Q₂ + 2Q₁ + Q₀

Which one of the following is the. correct state sequence of the circuit?

The following diagram represents a finite state machine which takes as input a binary number from the least significant bit

Which one of the following is TRUE?

Consider the following circuit

The flip-flops are positive edge triggered DFFs. Each state is designated as a two bit string Q₀Q₁ Let the initial state be 00. The state transition sequence is:

Consider the figure given below:

Initially all flip-flops are cleared. How many dock pulse have to be applied to the system before the output from FF3 becomes a HIGH level?

The logic circuit shown below is a 3-bit

The inputs of the J-K flip-flop, shown below are:
PRESET = CLEAR = 1; J = K = 0
If a single clock pulse is applied the device will

Let a_n a_n-1 ... a₁ a₀ be the binary representation of an integer b. The integer b is divisible by 3 if