Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  Test: Secondary Memory & DMA- 2 - Computer Science Engineering (CSE) MCQ

Test: Secondary Memory & DMA- 2 - Computer Science Engineering (CSE) MCQ


Test Description

8 Questions MCQ Test - Test: Secondary Memory & DMA- 2

Test: Secondary Memory & DMA- 2 for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Test: Secondary Memory & DMA- 2 questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Secondary Memory & DMA- 2 MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Secondary Memory & DMA- 2 below.
Solutions of Test: Secondary Memory & DMA- 2 questions in English are available as part of our course for Computer Science Engineering (CSE) & Test: Secondary Memory & DMA- 2 solutions in Hindi for Computer Science Engineering (CSE) course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: Secondary Memory & DMA- 2 | 8 questions in 25 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
Test: Secondary Memory & DMA- 2 - Question 1

Memory mapped I/O involves

Detailed Solution for Test: Secondary Memory & DMA- 2 - Question 1

Memory-mapped I/O performing I/O between CPU and peripheral devices (I/O) in a computer. In memory mapped I/O uses same address space to address both memory and I/O i.e. some address are reserved for I/O devices and rest used for memory. So it works in same way as b/w CPU and memory.

Test: Secondary Memory & DMA- 2 - Question 2

Compare the following by considering data transfer rate:
1. I/O processor
2. Data communication processor

Detailed Solution for Test: Secondary Memory & DMA- 2 - Question 2

A data communication processor communicates with each terminal through a single pair of wires. Both data and control information are transferred in a serial fashion with the result that the transfer rate is much slower as compare to input output processor.

1 Crore+ students have signed up on EduRev. Have you? Download the App
Test: Secondary Memory & DMA- 2 - Question 3

Consider a Disk I/O transfer, in which 1500 bytes are to be transferred, but number of bytes on a track is 1000, and rotation speed of disk is 1500 rps but the average time required to move the disk arm to the required track is 15 ms, then what will be total access time?

Detailed Solution for Test: Secondary Memory & DMA- 2 - Question 3


Given:
Ta→ transfer time T
s → average seek time =15 ms
r → rotation speed in rpms = 1500 rps
b → number of bytes to be transferred = 1500 bytes
N → num ber of bytes on a track = 1000 bytes

Test: Secondary Memory & DMA- 2 - Question 4

The computer can execute 1,000,000 instructions per second: A program running on this computer performs on average a one sector read and one sector write for every 200 instructions that it executes. The disk drive handling the I/O transfers requires 0.00010 seconds each to perform the read and write operations. Assuming no overlap of these operations, the percent of CPU time spent in the wait state is

Detailed Solution for Test: Secondary Memory & DMA- 2 - Question 4

•  The response time of I/O devices are magnitude order slower than that of CPU, hence direct interfacing is impossible.
• It is always better to off load the I/O processing to a secondary processor on the I/O controller board then to depend on the primary CPU for I/O processing.
• The variety of I/O devices in the market, requires that separate I/O controller exist for each device.

Test: Secondary Memory & DMA- 2 - Question 5

In a general purpose computer system the CPU, the main memory and the cache may be interconnected via one or more shared system bus(es). However, input/output devices (eg. Hard disk, network interfaces) may only be connected to the system bus through an I/O controller. The following are four statements regarding the requirement for an I/O controller.
1. The capacities of I/O devices are magnitude order larger than that of main memory and hence direct interfacing is impossible.
2. The response times of I/O devices are magnitude order slower than that of CPU and hence direct interfacing is impossible.
3. It is always better to off load the I/O processing to a secondary processor on the I/O controller board then to depend on the primary CPU for I/O processing.
4. The variety of I/O devices in the market requires that a separate I/O controller exist for each device.

Q. What statement(s) best explain the requirement for an I/O controller?

Test: Secondary Memory & DMA- 2 - Question 6

An 8-Bit DMA Device is operating is Cycle Stealing Mode (Single Transfer Mode). Each DMA cycle is of 6 clock states and DMA clock is 2 MHz. Intermediate CPU machine cycle takes 2 μs, determine the DMA Data Transfer Rate

Detailed Solution for Test: Secondary Memory & DMA- 2 - Question 6

DMA Clock is 2 MHz ⇒ Each DMA Clock state is 0.5μs 
Each DMA Cycle has 6 Clock States ⇒ Each DMA cycle is of 3 μs
In Cycle Stealing 1 CPU and 1 DMA Cycles run alternately and the CPU Cycle takes 2 μs.
Therefore, every 3 + 2 = 5 μs, 1 byte is transferred by DMA device.
Data Transfer Rate = 1000000/5 x 1 Byte
= 200 Kbytes / Sec

Test: Secondary Memory & DMA- 2 - Question 7

A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte- wise. Let the interrupt overhead be 4 μsec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program controlled mode?

Detailed Solution for Test: Secondary Memory & DMA- 2 - Question 7


Test: Secondary Memory & DMA- 2 - Question 8

Consider a disk drive with the following specifications: 16 surfaces, 512 tracks / surface, 512 sectors / track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is

Detailed Solution for Test: Secondary Memory & DMA- 2 - Question 8

Revolution Per minute = 3000 RPM 
or 3000/60 = 50 RPS
In one track rotation it can read = 512 KB
In 50 RPS it can read = 512 x 50

⇒ For 4 bytes it takes 156 ns

Percentage of time that the CPU gets blocked
during DMA operation 

Information about Test: Secondary Memory & DMA- 2 Page
In this test you can find the Exam questions for Test: Secondary Memory & DMA- 2 solved & explained in the simplest way possible. Besides giving Questions and answers for Test: Secondary Memory & DMA- 2, EduRev gives you an ample number of Online tests for practice

Top Courses for Computer Science Engineering (CSE)

Download as PDF

Top Courses for Computer Science Engineering (CSE)