Electrical Engineering (EE) Exam > Electrical Engineering (EE) Tests > Test: Sequential Logic Circuits- 2 - Electrical Engineering (EE) MCQ

Test Description

Test: Sequential Logic Circuits- 2 for Electrical Engineering (EE) 2024 is part of Electrical Engineering (EE) preparation. The Test: Sequential Logic Circuits- 2 questions and answers have been prepared
according to the Electrical Engineering (EE) exam syllabus.The Test: Sequential Logic Circuits- 2 MCQs are made for Electrical Engineering (EE) 2024 Exam.
Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Sequential Logic Circuits- 2 below.

Solutions of Test: Sequential Logic Circuits- 2 questions in English are available as part of our course for Electrical Engineering (EE) & Test: Sequential Logic Circuits- 2 solutions in
Hindi for Electrical Engineering (EE) course.
Download more important topics, notes, lectures and mock test series for Electrical Engineering (EE) Exam by signing up for free. Attempt Test: Sequential Logic Circuits- 2 | 15 questions in 45 minutes | Mock test for Electrical Engineering (EE) preparation | Free important questions MCQ to study for Electrical Engineering (EE) Exam | Download free PDF with solutions

1 Crore+ students have signed up on EduRev. Have you? Download the App |

Test: Sequential Logic Circuits- 2 - Question 1

Assertion (A): The indeterminate condition of the J-K flip-flop is permitted in S-R flip-flop.

Reason (R): A J-Kfiip-flop has a characteristic similar to that of an S-R flip-flop.

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 1

Test: Sequential Logic Circuits- 2 - Question 2

The J-K master-slave flip-flops in figure shown below has its J and K inputs tied to + V_{CC} and a series of pulses is applied to its CLK input.

The waveform at G is given by

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 2

Test: Sequential Logic Circuits- 2 - Question 3

For the J-Kflip-flop shown below to function as a divide-by-2 element, the J and K inputs should be equal to

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 3

Test: Sequential Logic Circuits- 2 - Question 4

Match List-l with List-II and select the correct answer using the codes given below the lists:

List-I

A. J-K flip-flop

B. D flip-flop

C. Master-slave flip-flop

D. T flip-flop

List-lI

1. Transparent latch

2. Most versatile and widely used of all the flip flops

3. Not widely available as commercial items

4. Pulse triggered flip-flop

Codes:

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 4

Test: Sequential Logic Circuits- 2 - Question 5

Assertion (A): An unclocked flip-flop is called a latch.

Reason (R): A latch is constructed using two cross-coupled NAND gates or NOR gates.

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 5

Test: Sequential Logic Circuits- 2 - Question 6

Consider the following statements associated with flip-flops;

1. Any one type of flip-flop can be converted to any other type by providing a suitable combinational circuit.

2. The inputs to a master-slave flip-flop must change when the clock is HIGH.

3. In a master-slave flip-flop, master is level triggered while slave is edge triggered.

4. Data lock-out flip-flops are nothing but master-slave flip-flops.

Q. Which of the statements given above is/are not correct?

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 6

Test: Sequential Logic Circuits- 2 - Question 7

For the flip-flop shown below, there is one clock pulse for each bit time.

If the following serial data are applied to the flip-flop, then the resulting decimal value of the serial data that appears on the Q output will be (assume that, Q is initially ‘0’)

J_{1} = 01101101 ; J2 =10011011

K_{1} = 01101001 ; K_{2} = 11011011

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 7

Test: Sequential Logic Circuits- 2 - Question 8

For a flip-flop formed from two NOR gates as shown in figure the unusable state corresponds to

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 8

Test: Sequential Logic Circuits- 2 - Question 9

The digital circuit as shown below represents to which one of the following?

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 9

Test: Sequential Logic Circuits- 2 - Question 10

If t_{p} is the pulse width, Δt is the propagation delay, T is period of pulse train then which of the following condition can avoid the race around condition?

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 10

Test: Sequential Logic Circuits- 2 - Question 11

Match List-I (Logic Circuit) with List-ll (Circuit Realization) and select the correct answer using the codes given below the lists:

List-I

A. J-K flip-flop

B. T flip-flop

C. D fiip-flop

List-ll

Codes:

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 11

Test: Sequential Logic Circuits- 2 - Question 12

The characteristic equation of a T flip-flop is given by

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 12

Test: Sequential Logic Circuits- 2 - Question 13

In a J-Kflip-flop we have (shown in figure). Assuming the flip-flop was initially cleared and then clocked for 6-pulses, the sequence at the Q output will be

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 13

Test: Sequential Logic Circuits- 2 - Question 14

The output of a J-Kflip-flop Q_{n} is ‘0’. The state of the flip-flop changes when a clock pulse is applied. The possible combination of J_{n} and K_{n} inputs could be (‘X' denote don’t care)

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 14

Detailed Solution for Test: Sequential Logic Circuits- 2 - Question 15

Information about Test: Sequential Logic Circuits- 2 Page

In this test you can find the Exam questions for Test: Sequential Logic Circuits- 2 solved & explained in the simplest way possible.
Besides giving Questions and answers for Test: Sequential Logic Circuits- 2, EduRev gives you an ample number of Online tests for practice

Download as PDF