Test: Sequential Logic Circuits- 2 - Electrical Engineering (EE) MCQ

The truth table for S-ffand J-Kflip-flop are shown below.

It is clear from the above truth table that when S = R = 1, the output of S-R flip-flop is indeterminate. However, when J = K = 1, the output of J-Kflip-flop is (not indeterminate). Therefore, the indeterminate condition of the S-R flip-flop is permitted in a J-Kflip-flop.
A J-Kflip-flop has a characteristic similar to that of an S-R flip-flop which is evident from the above truth tables.
Hence, assertion is false but reason is true.

Let the flip-flop is initially reset.
The truth table for aiven circuit is shown below

Thus, the waveform for Q will be as shown below

If J = K = 1, then the truth table will be as show below (Initially flip-flop is.reset).

Thus, the given J-Kflip-flop will work as a divide- by-2 elemen

• The J-K flip-flop is the most versatile and most widely used of all the flip-flops.
• Transparent latch is associated with D-flip flop since the clocked D latch is called a transparent D latch, because its output follows the input when the clock is HIGH.
• Master-slave flip-flops are called pulse- triggered flip-flops, because the length of time required for its output to change state equals the width of one (clock) pulse.
• T flip -flop is not widely available as commercial items.

An unclocked flip-flop is called a latch, because the output of the flip-flop latches on to ‘1’ or ‘0' immediately after the input is applied. Hence, assertion is a correct statement. Reason is also a true statement but not the correct explanation of assertion.

• Statement-1 is correct.
• The inputs to a master-slave flip-flops must not change when the clock is HIGH. If they change, the flip-flop gives an output corresponding to the last combination of inputs present before the dock terminals. Hence, statement-2 is not correct.
• In a master-slave flip-flop, master is edge-triggered while slave is level triggered. Thus, statements-3 is not correct.
• Data lock-out flip-flops are nothing but master-slave flip-flops in which the master is an edge triggered flip-flop. Thus, statement-4 is correct.

Q = 0 (Initially)

Thus, serial output data at Q
= 00001110 = 14 (Decimal value)

Given flip-flop represents S-R latch using NOR gates.
When A = 1, B = 1 we will get invalid or unusable state.

Here, 
If X = S and Y = R then, the given circuit circuit represents S-R flip-flop using D flip-flop

Race around condition occurs in J-K flip-flop when J = K = 1. This condition can be avoided if the propagation delay of flip-flop is more than pulse-width of the clock but less than the clock.
i.e. 2t_p < Δt < T

For conversion of S-R flip-flop to
A. J-K flip flop:
S = JQ' and R = KQ
B. T Flip-flop:
S = TQ' and = TQ
C. D flip-flop:

For a T flip-flop, Q_n+1 = 

The truth table will be as shown below.

Thus, output Q for 6 clock pulse = 101010.

The truth table of J-K flip-flop is shown below.

Given, Q_n = 0 initially,
When clock pulse is applied, the state of FF changes to ‘1’ i.e. Q_{n+ 1} = 1, which is possible,
if, ' J = 1, K = 0 ...(i)
or, J_n = 1 , K_n = ‘X’ ...(ii)
Thus, J_n = 1 and K_n = ‘X (don't care) satisfy the above two conditions.

A FF is set when Q = 1, 
A FF is reset when  Q = 0 ;