Test: T Flip Flop - Electrical Engineering (EE) MCQ

The characteristic equation for various flip flops is shown:

• SR flip flop

Qn + 1 = S + R’Q

• J-k flip flop

Qn + 1 = JQ’ + K’Q

• D flip flop

Qn + 1 = D

• T flip Flop

Qn + 1 = T exor Q = T’Q +TQ’

Calculation:

Q(t + 1) = Q(t) ⊕ X

& for T F/F

Q(t + 1) = Q(t) ⊕ T

Concept:

For a counter with ‘n’ flip flops:

• The total number of states = 2n (0 to 2n – 1)
• The largest number that can be stored in the counter = 2n – 1

To construct a counter with any MOD number, the minimum number flip flops required must satisfy:

Modulus ≤ 2n

Where n is the number of flip-flops and is the minimum value satisfying the above condition.

Calculation:

The total number of states required when n = 3:

23  ≥  8

The states will vary from (0 to 7)

So the maximum states possible for the counter will be 8.

D flip flop:

D flip flop has only one input terminal. The output of the D flip flop will be the same as the input. Hence, it is used in delay circuits.

The circuit is as shown below.

Logic symbol:

Truth table:

Characteristic equation: Qn+1 = D

The D flip flop may be obtained from an S-R flip flop by just putting one inverter between the S and R as shown in the figure below.

S = R̅

The D flip flop may be obtained from a J-K flip flop by just putting one inverter between the J and K as shown in the figure below.

K = J̅

T flip flop:

T flip flop has only one input terminal. The output of the T flip flop will be toggled when the input is high on every new clock pulse. The output will be the same as the previous state when the input is low.

The circuit is as shown below.

Logic symbol:

Truth table:

Characteristic equation: Qn+1 = TQ̅­n + T̅Qn

The T flip flop may be obtained from a J-K flip flop by making both the inputs are the same i.e. J = K.

Concept:

If we pass the input signal to a single T-flip flop, we will get half of the frequency at the output.

Similarly, when we pass the input signal into an n-bit flip flop counter, the output frequency (fout) will be:

Given Input frequency f = 1 kHz

f_out = 125 Hz

T Flip Flop MCQ Question 9 Detailed Solution

From the above table we observe that before the start of the next clock pulse, the inputs are:

J = 1, K = 0, T = 1

The output after the first clock pulse will be:

Q_A Q_B = 11

The inputs are now:

J = 0, K = 1, T = 1

The output after the second clock pulse will be:

Q_A Q_B = 00

The inputs are now:

J = 1, K = 0, T = 0

The output after the third clock pulse will be:

Q_A Q_B = 10

The given circuit is in toggle mode, so frequency will get half.

Output frequency = 0.5 kHz

If we pass the input signal to a single T-flip flop, we will get half of the frequency at the output.

Similarly, when we pass the input signal into an n-bit flip flop counter, the output frequency (fout) will be:

Given Input frequency f = 200 Hz

f_out = 25 Hz

Concept:

T flip-flop

The truth table of the T flip-flop is given by:

The characteristic table of the T flip-flop is:

The characteristic equation of the T flip-flop is:

Q(t + 1) = T ⊕ Q(t)

Analysis:

From the given circuit two flip-flops are present and the Q₁’ output is connected to the input of the second flip-flop.

T₂ = Q₁’

Given circuit is an example of the Down counter.

The below figure represents the waveforms for the respective clock edges.

The flip-flop2 will trigger only when the Q₁’ is going from 0 to 1, i.e., positive triggering of the Q₁’.

In the output is Q₁ the total time period is 4 times that of the clock (4T).

Conclusion:

As the time period is 4 times then the frequency will be divided by four times.

f_out = 0.25 MHz = 250 kHz

T flip-flop allows the same inputs. So, in J-K flip-flop J=K then it will work as T flip-flop.

Both flip-flop and latches are memory elements with clock/control inputs. They depend on the past as well as present states. Whereas, in case of combinational circuits, they only depend on the present state.

The SR latch is the basic block for the D latch/flip flop from which the JK and T flip flops are derived. A latch is similar to a flip-flop, only without a clock input.

RS-232 only allows for one master and one slave and is limited to distances of up to 15 meters.

Key Points 
RS-232, RS-422, and RS-485 are standards for serial communications that define the pinouts, cabling, signal levels, transmission baud rates, and parity checking.

• RS-232 only allows for one master and one slave and is limited to distances of up to 15 meters.
• RS-422 can address up to 10 slaves using four wires (full duplex) and has a distance capacity of 4000 feet.
• RS-485 can address up to 32 slaves using either a two-wire (half duplex) or a four-wire system (full duplex) and has a distance capacity of 4000 meter

Combinational circuits are often faster than sequential circuits. Since the combinational circuits do not require memory elements whereas the sequential circuits need memory devices to perform their operations in sequence. Latches and Flip-flops come under sequential circuits.

Trigger pulse is defined as a pulse that starts a cycle of operation.

The input at which the flip flop changes its state when synchronized with the clock is called the synchronous control inputs. For T flip flop T is the synchronous control input.