Test: (Junction Field Effect Transistor) JFET - 1 - Electronics and Communication Engineering (ECE) MCQ

BJT usually are built with a thickness of up to 1cm whereas the FET uses a fabrication technique which makes its size in mm.

For a FET the current reaches maximum that is IDSS occurs when V_gs = 0V and V_DS > = |V_p|

By using the diode equation Shockley derived the equation between the drain current and voltage V_gs.

By varying the gate to source voltage, Resistance can be varied as follows r_d = r_o/(1-V_gs/V_p)²

When the voltage is lesser than pinch off, the current flows from Source to Drain.
The forward bias drain and gate is the reason for the flow of electron from Drain to source, as the conventional current flows opposite to the electron flow, the current will flow from Source to Drain.

Because of the Sio2 insulator, doped between drain and source at the top, the resistance offered by this is very high. The insulator will stop the flow of electron from one part to another which acts as an open circuit.

Because of its small size, the IC chips can be made even smaller which reduces the wear and tear. The process technology used with process technology constant a which is the ratio of Width and Length, the FET is made more advantageous.

When the gate to source voltage is less than pinch off, both of the junctions will be reverse biased and hence no current flows.

I_D = I_DSS (1-V_gs/V_p)²
If V_gs = V_p,then
I_D = I_DSS (1-1)=0.

When a voltage greater than pinch off is applied, the current starts flowing from Drain to source.