Test: Triggering of Flip Flops - GATE MCQ

Edge triggered device will follow the input condition when there is a transition. It is said to be positive edge triggered when transition occurs from LOW to HIGH. While it is said to be a negative edge triggered when a transition occurs from HIGH to LOW.

The half circle on the clock input of a J-K flip-flop mean level triggered. Whereas the presence of triangle symbol implies that the flip-flop is edge-triggered.

The circle on the clock input of a J-K flip-flop mean negative edge triggered. Whereas the absence of triangle symbol implies that the flip-flop is level-triggered.

Unlike the SR latch, these circuits have no invalid states. The SR latch or flip-flop has an invalid or forbidden state where no output could be determined.

Active low indicates that only an input value of 0 sets or resets the circuit.

The two stable states of combinational circuits are 1 and 0. Whereas, in flip-flops there is an additional state known as Forbidden State.

T flip-flop allows the same inputs. So, in J-K flip-flop J=K then it will work as T flip-flop.

A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table. The characteristic equation of J-K flip-flop is given by: Q(n+1)=JQ'(n)+K’Q(n).

As one flip flop is used so there are two states available. So, 20/2 = 10Hz frequency is available at the output.

The direct line on the clock input of a J-K flip-flop mean level triggered. Whereas the presence of triangle symbol implies that the flip-flop is edge-triggered.