Shift Registers - GATE ECE Engineering (ECE) Digital Circuits Free MCQ

One clock period is = (1⁄2) micro-s = 0.5 microseconds. In serial transmission, data enters one bit at a time. So, the total delay = 0.5*8 = 4 micro seconds time is required to transmit information of 8 bits.

Concept: A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for each data bit. The output from each flip-Flop is connected to the D input of the flip-flop at its right. Shift registers hold the data in their memory which is moved or “shifted” to their required positions on each clock pulse.

Calculation: If four data bits are shifted in by four clock pulses via a single wire at data-in, below, the data becomes available simultaneously on the four Outputs Q_A to Q_D after the fourth clock pulse.

After 3 clock cycles, the output will be 0101

LSB bit is inverted and feed back to MSB:
01110->initial
10111->first clock pulse
01011->second
00101->third.

Because no other flip-flops are connected with the output Q, therefore one can use the Q out of each FF to take out parallel data.

SIPO stands for Serial-in Parallel-out, which is a type of digital shift register. This configuration allows for data to be inputted serially (one bit at a time) and then outputted in parallel (multiple bits simultaneously). The key characteristics include:

• Data Input: Bits are entered one after another.
• Data Output: All bits can be accessed at once.
• Application: Commonly used in digital circuits for data storage and transfer.

f = 200 KHZ; T = (1/200) m sec = (1/0.2) micro-sec = 5 micro-sec;
In serial transmission, data enters one bit at a time. After 8 clock cycles only 8 bit will be loaded = 8 * 5 = 40 micro-sec.

In Serial-In/Serial-Out shift register, data will be shifted one at a time with every clock pulse. Therefore,
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.

At Preset condition, outputs of flip-flops will be 1. Preset = 1 means Q = 1, thus input is definitely 1.

A shift register can shift it’s data either left or right. The universal shift register is capable of shifting data left, right and parallel load capabilities.

The registers in which data can be shifted serially or parallelly are known as shift registers. Based on how binary information is entered or shifted out, shift registers are classified into 4 categories, viz., Serial-In/Serial-Out(SISO), Serial-In/Parallel-Out (SIPO), Parallel-In/Serial-Out (PISO), Parallel-In/Parallel-Out (PIPO).