Cache Memory - Computer Science Engineering (CSE) MCQ

The transfer is a word transfer. In the memory subsystem, word is transferred over the memory data bus and it typically has a width of a word or half-word.

This happens in the associative mapping. In this case, a block of data from the main memory can be mapped anywhere in the cache memory.

There is no policy which is called as the write within policy. The other three options are the write policies which are used to avoid cache coherence.

LRU stands for Least Recently Used. LRU is a type of replacement policy used by the cache memory.

There is only 1 sign bit in all the standards. In a 32-bit format, there is 1 sign bit, 8 bits for the exponent and 23 bits for the mantissa.

Snoopy writes is the efficient method for updating the cache. In this case, the cache controller snoops or monitors the operations of other bus masters.

The cache is said to be inconsistent. Inconsistency must be avoided as it leads to serious data bugs.

Whenever the data is found in the cache memory, it is called as Cache HIT. CPU first checks in the cache memory since it is closest to the CPU.

It is called the Cache Memory. The cache memory is the high speed memory between the main memory and the CPU.

The Cache memory is implemented using the SRAM chips and not the DRAM chips. SRAM stands for Static RAM. It is faster and is expensive.