Test: Sequential Circuits - Computer Science Engineering (CSE) MCQ

Concept:
For a counter with ‘n’ flip flops:

• The total number of states = 2n (0 to 2n – 1)
• The largest number that can be stored in the counter = 2n – 1
   

To construct a counter with any MOD number, the minimum number flip flops required must satisfy:
Modulus ≤ 2n
Where n is the number of flip-flops and is the minimum value satisfying the above condition.

Calculation:
The total number of states required when n = 3:
23  ≥  8
The states will vary from (0 to 7)
So the maximum states possible for the counter will be 8.

01111111 → 127
After 135 clock cycles, we will get
127 + 135 = 262
∴ The total number of clock pulses will be 262
As the modulus is 256,
After 256 clock pulses, the sequence will repeat.
262 = 256 + 6
∴ 00 00 00 00
257 → 00 00 00 01
258 → 00 00 00 10
259 → 00 00 00 11
260 → 00 00 01 00
261 → 00 00 01 01
262 → 00 00 01 10

• Combinational logic is a type of digital logic that is implemented by Boolean circuits, where the output is a pure function of the present input only.
• Sequential logic is a type of digital logic in which the output depends not only on the present input but also on the history of the output.
• Sequential logic has memory while combinational logic does not.
• Flip-flop, counter, and shift registers are sequential circuits whereas multiplexer, decoder, and encoder act like combinational circuits.

Concept:
digital frequency counters that use a direct counting approach count the number of times the input signal crosses a given trigger voltage (and in a given direction, e.g. moving from negative to positive) in a given time. This time is known as gate time.
The frequency is equal to the number of crossings of the trigger level in one second. Therefore
Frequency(f)=Triggerl evel crossing (N)/Gatetime(t)
Percentage accuracy of the counter= (N−1/N) × 100
Calculation:
Given;
Gate time = 2 sec
Frequency = 40 Hz
Then;
Frequency(f)=Trigger level crossing(N)/Gatetime(t)
Trigger level crossing (N) = Frequency (f) ×Gate time(t)=40 × 2 = 80
Hence;
Percentageaccuracyofthecounter=(N−1/N) × 100= (80−1/80) × 100 = 98.75
Hence, option b is the correct answer.

Concept:
Digital frequency counters that use a direct counting approach count the number of times the input signal crosses a given trigger voltage (and in a given direction, e.g. moving from negative to positive) in a given time. This time is known as gate time.
The frequency is equal to the number of crossings of the trigger level in one second. Therefore
Frequency=Trigger level crossing/Gatetime
Calculation:
Given;
Gate time = 2 sec
Frequency = 30 Hz
Then;
Frequency=Trigger level crossing/Gatetime
∴Trigger level crossing = frequency × gate time = 30 × 2 = 60

The given sequential component is of RS Flip Flop.
Here A = R and B = S

The truth table for the circuit is shown:

The Ring shift counter is a recirculating register in which the serial output is connected back to the serial input as shown:

A Straight ring counter with ‘n’ flip-flops will have n states.

Concept:
D-flipflop is a flipflop that produces a delay of exactly one cycle to the CLK.

The characteristic equation of a D flip flop is:
Q_n+1 = D
It is also known as ‘’Transparent latch” because Qn+1 = D
Application:
From given sequential circuit:
and D₁ = Q₀
Now,

So, counts state (Q₁ Q₀) follows the sequence:
00 → 01 → 10 → 00 → 01 ….

Concept:
It is an active low signal. It is activated when =0 and it resets the FF.
CLR: It is an active high signal. It is activated when CLR = 1 and it Resets the FF.

• Synchronous: Synchronous clear is synchronized with the clock. It waits for a clock pulse to Reset FF output.
• Asynchronous: Asynchronous Clear is not synchronized with the clock. It does not wait for a clock pulse to Reset FF output.

Application:
From given sequential circuit:

When both QB & QC equal to 1 then =0. Otherwise = 1
Now,

Since it is given that the counter have synchronous clear input, the output of the counter will reset at the 7th clock pulse.
∴ The mod of the counter, n = 7

A sequence detector is a sequential circuit that outputs 1 when a particular pattern of bits sequentially arrives at its data input.
Given input data = 1,1,0,1,0,0,1,1,0,1,0,1,1,0
Overlapping sequences detectable.
The below table shows the output for each sequence.


The output = 0,1,0,0,0,0,0,1,0,1,0,0