Combinational Circuits - GATE CSE (CSE) Digital Logic Free MCQ Test

ECL (Emitter Coupled Logic):
It is fast then all logic family and very high speed in ECL transistor use in differential amplifier configuration
When a transistor is operated in a saturation condition, due to the charge stored in the collector and base regions, it turns ON or OFF slowly. This drawback has been eliminated in ECL by operation the transistor only in the active or off region.

A 64 × 1 multiplexer has 64 inputs so if we use 2 × 1 multiplexers 32 are needed in the first stage for 64 inputs, the output of these 32 multiplexers are connected to inputs of 16 multiplexers in the second stage.
Similarly, in third stage, 8 (2 × 1) multiplexers are used, in fourth stage 4 are used and finally 2 (2 × 1) multiplexers in the fifth stage, 1 in the sixth stage.
Total 2 × 1 multiplexers needed are 32 + 16 + 8 + 4 + 2 + 1 = 63.

Concept:
A universal gate is the one with which any other Boolean function can be implemented without the need of other gates.

Explanation:
Two universal gates are NAND and NOR.
NAND:
In this gate, output of logic gate is false only when both the inputs are true. It is the complement of AND gate.
NOR gate: Output of this logic gate is true when both inputs are false.
Truth Table:

Full Adder is a combinational circuit with 3 input bits and 2 output bits CARRY and SUM. Three bits full adder requires 2³ = 8 combinational circuits.

In the given diagram, S0 and S1 are selection bits. So,
I/P S0 S1 O/P
D = 0 0 0 Y0
D = 0 0 1 Y1
D = 0 1 0 Y2
D = 0 1 1 Y3
Hence, inputs are S0 and S1 are Low means 0, so output is Y0 and rest all are HIGH.

Short to ground in the output of a driving gate indicates of a signal loss to all load gates. This results in information being disrupted and loss of data.

When both inputs are same then the o/p is high for a XNOR gate.
i.e., A B O/P
0 0 1
0 1 0
1 0 0
1 1 1.
Thus, it will produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is odd number of 1s.

The given diagram is demultiplexer, because it takes single input & gives many outputs. A demultiplexer is a combinational circuit that takes a single output and latches it to multiple outputs depending on the select lines.

This happens in parallel adders (where we try to add numbers in parallel via more than one. There is the slight delay in next adder and this is known as carry propagation.

For decoding any binary data, output must be high for that data (code) and thus is possible in one 4-input AND gate, one inverter option only.
A decoder is a combinational circuit that converts n− bit binary coded data upto 2ⁿ outputs.