GATE Computer Science Engineering(CSE) 2027 Test: Circuit Outputs Free

There are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the presence of a clock signal, whereas, Asynchronous Sequential Circuits function in the absence of a clock signal.

circuit behaves as shift register and mod6 counter
clock cycle    output
1                    100
2                    110
3                    111
4                    011
5                    001
6                    000

EDIT- This is Johnson counter which is application of Shift Register. And Johnson counter is  mod 2N  counter.

(((AB)' C)' (CD)')' = ((AB)'C) + CD) = (A' + B')C + CD = A'C + B'C + CD

when b3b2 is 11 restore circuit to 0000..
it counts from 0 to 11 i.e. Radix 12 no ..
circuit used for  binary to radix 12 conversion..

Options for this question seem wrong, its expression f will come to A'B'C + A'BC + AB'C + ABC, that further can be minimized to C.

Since are in canonical sum of products form, will only contain their common terms- that is

The figure is not clear- I assume there is a NOT gate just before taking Y making the final AND gate a NAND gate.
We have a steady state- meaning output is not changing. Y is 1 and remains 1 in the next state(s). So, we can write

Here clocks are applied to both flip flops simultaneously
When 11 is applied to jk flip flop it toggles the value of P so op at  P will be 1
Input to D flip flop will be 0( initial value of P)  so op at Q will be 0
So ans is a

Given clock is + edge triggered.
See the first positive edge. X is 0, and hence output is 0. Q₀ is 1 and Q₀' is 0.
Second + edge, X is 1 and Q0' is also one. So, output is 1. (When second positive edge of the clock arrives, Q₀' would surely be 1 because the set up time of flip flop is given as 20 ns and the clock period is >= 40 ns)
Third + edge, X is 1 and Q₀' is 0, So, output is 0. (Q₀' becomes 0 before the 3rd positive edge, but output Y won't change as the flip flop is positive edge triggered)
Now, output never changes back to 1 as Q₀' is always 0 and when Q₀' finally becomes 1, X is 0.
Set up time and hold times are given just to ensure that edge triggering work properly.

As X connected to I₀ & I₁ .Y connected to I₂, Y' connected to I₃ & A1 , Z connected to A₀ and Z' connected to ENABLE (EN).

F = (XYZ' +XYZ + Y'ZY + ZY')Z'
= (XYZ' +XYZ + ZY')Z'
=XYZ'

sequence is

From the given sequence, we have state table as 

Now we have present state and next state, use excitation table of T flip-flop 

The expression will be
f = [(x.y')'.(y.z)]'=[(x'+y).(y.z)] =[x'.y.z+y.z]'=[(x'+1).(y.z)]'=[1.(y.z)]'=[y.z ]'=y'+z'
The final expression only contains y and z,
Therefore, answer will be (a) f is Independent of x

D = AX + X'Q'
Y = D
Ai represent the logic level on the line A at the i-th clock period. If we see the timing diagram carefully, we can see that during the rising edge, the output Y is determined by the X value just before that rising edge. i.e., during the rising edge say for clk2, X value that determines the output is 1 and not 0 (because it takes some propagation delay for the 0 to reach the flip flop). Similarly, the A output that determines the output for clk i, is A_i-1
For clk1, X is 1, so, D = A = A₀
For clk2, X is 1, so D = A = A₁
For clk 3, X is 0, so D = Q2' = A₁'
For clk4, X is 1, so D = A = A₃
For clk5, X is 1, so D = A = A₄
So, answer is A choice.

Clearly Q₀ alternates in every clk cycle as Q₀' is fed as input and it is D flipflop.

Q₁ becomes 1 if its prev value and current Q₀ differs (EXOR).
So, the sequence of transitions will be 00 -> 11 -> 01 -> 10 -> 00 (D) choice.  

If it's looked carefully, bulb will be on when both switch s1 and s2 are in same state, either off or on. that is exnor operation
S1 S2  Bulb
0   0    On
0   1    Off
1   0    Off
1   1   On
it's Ex-NOR operation hence (C) is the correct option.

The filling is done in reverse order. Here, none of the options matches. So, something wrong somewhere. 

if you solve this you will get XY' + Y'Z + XY (this can be simplified to X + Y'Z) with min terms as (1,4,5,6,7)
and option A has the same min terms
so option A is equivalent to XY' + Y'Z + XY

Result of MUX (first one), is,say f1, = xz'+ y'z
Result of MUX(second one , f= f1y' +xy
=(xz'+y'z)y'+xy  = xy'z' +y'z +xy =x(y'z' +y) +y'z  = x(y'+y)(z'+y) +y'z   =xz'+xy+y'z .
Option A.
Note:
1. f =I0S' +I1S ,for 2:1 MUX , where I0 and I1 are inputs , S is select line 2. Distributive property , A+BC = (A+B)(A+C)
3. A+A' =1

whenever  A4 A3 A2 A1 =0 1 0 1 then clear line will be enabled as A3 and A1 set.
given table says that whenever clear control signal set , it clears to 0 0 0 0 , before the current clock cycle completes.
so 5 is cleared to 0 in the same clock cycle.
so counter sequence is 0, 1 , 2, 3, 4

the final answer will come as --
a'+c'+d'+a'c+ab+bc
= a'(c+1)+c'+d'+ab+bc
=a'+c'+d'+ab+bc
=(a'+a)(a'+b)+(c'+c)(c'+b)+d' =a'+b+c'+b+d'
=a'+b+c'+d'

To detect the fault, we should get an unexpected output. The final gate here is a NOR gate which produces output 0 if either of its input is 1 and else 1. i.e., the output will be 0 for inputs  and  and output will be 1 for (0,0).
By grounding T is at 0. So, we can ignore the inputs (1,0) and (0,0) to the final NOR gate as they won't be detecting faults. Now, expected (1,1) input will become (1,0) due to grounding of T but produces same output 0 as for (1,1).
Hence this also cannot detect the defect. So, to detect the defect, the input to the final gate must be (1,1) which is expected to produce a 0 but will produce a 1 due to grounding of T.

Now, for (0,1) input for the final gate, we must have,

, the OR gate makes 1 output and we won't get  input for the final gate. This means, no input sequence can detect the fault of the circuit.
Alternatively, we can write equation for the circuit as

For the faulty circuit output will be

So, there is no effect of T being grounded here. Answer is D option.

The four bit register contains: 1011, 1101, 0110, 1011, 1101, 0110 after each shift.

F = (x'z' + xz)' = xz' + x'z

Initially Q0Q1 = 00
after first clock signal Q0 will be toggled and change to 1. It will activate clock of second FF in sequence and toggle that one as well.
Hence next output Q0Q1=11
Similarly next few sequences for Q0Q1 will be 01, 00
Hence answer sequence Q1Q0 will be 11,10,01,00