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GATE Computer Science Engineering(CSE) 2027 Test: Synchronous & Asynchronous


MCQ Practice Test & Solutions: Test: Synchronous & Asynchronous Circuits (10 Questions)

You can prepare effectively for Computer Science Engineering (CSE) GATE Computer Science Engineering(CSE) 2027 Mock Test Series with this dedicated MCQ Practice Test (available with solutions) on the important topic of "Test: Synchronous & Asynchronous Circuits ". These 10 questions have been designed by the experts with the latest curriculum of Computer Science Engineering (CSE) 2026, to help you master the concept.

Test Highlights:

  • - Format: Multiple Choice Questions (MCQ)
  • - Duration: 30 minutes
  • - Number of Questions: 10

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Test: Synchronous & Asynchronous Circuits - Question 1

be a switching function. Which one of the following is valid?

Detailed Solution: Question 1

f(x,y,z) = x' + y'x + xz
An implicant of a function is a product term that is included in the function. so x', y'x and xz ,all are implicants of given function.
A prime implicant of a function is an implicant that is not included in any other implicant of the function.
option a)   y'x is not a prime implicant as it is included in xz [ xy'z+ xyz]
option d) y is not a prime implicant as it include in both x' and xz.
a product term in which all the variables appear is called a minterm of the function

Test: Synchronous & Asynchronous Circuits - Question 2

Which are the essential prime implicants of the following Boolean function?

Detailed Solution: Question 2

answer - A
using K map f = ac' + a'c

Test: Synchronous & Asynchronous Circuits - Question 3

A main memory unit with a capacity of 4 megabytes is built using 1M x 1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is

Detailed Solution: Question 3

There are 4*8 = 32 DRAM chips to get 4MB from 1M x 1-bit chips. Now, all chips can be refreshed in parallel so do all cells in a row. So, the total time for refresh will be number of rows times the refresh time

*Answer can only contain numeric values
Test: Synchronous & Asynchronous Circuits - Question 4

A ROM is used to store the Truth table for a binary multiple unit that will multiply two 4-bit numbers. The size of the ROM that is required to accommodate the Truth table is . Write the values of M and N.


Detailed Solution: Question 4

A is 4 bit binary no A4A3A2A1
B is 4 bit binary no B4B3B2B1
M is result of multiplication M8M7M6M5M4M3M2M1     [check biggest no 1111 x 1111 =11100001]

So 4 bit of A 4 bit of B
input will consist of 8 bit need address 00000000 to 11111111 = 28 address
output will be of 8 bits
so memory will be of
M = 256 , N = 8

Test: Synchronous & Asynchronous Circuits - Question 5

A ROM is used to store the table for multiplication of two 8-bit unsigned integers. The size of ROM required is

Detailed Solution: Question 5

When we multiply two 8 bit numbers result can go up to 16 bits. So, we need 16 bits for each of the multiplication result.
Number of results possible = 28 ⨯ 28 = 216 = 64 K as we need to store all possible results of multiplying two 8 bit numbers. So, 64 K ⨯ 16 is the answer. 

Test: Synchronous & Asynchronous Circuits - Question 6

What is the minimum size of ROM required to store the complete truth table of  multiplier?

Detailed Solution: Question 6

multiplying 2 8 bit digits will give result in maximum 16 bits
total number of multiplications possible = 28 x 28
hence space required = 64K x 16 bits

Test: Synchronous & Asynchronous Circuits - Question 7

The amount of ROM needed to implement a 4 - bit  multiplier is

Detailed Solution: Question 7

A ROM cannot be written. So, to implement a 4 bit multiplier we must store all the possible combinations of input bits and  output bits giving a total of . So, (D) is the answer.

Test: Synchronous & Asynchronous Circuits - Question 8

Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation?

Detailed Solution: Question 8

For R-S flip flop with NAND gates (inputs are active low) 11-no change 00-indeterminate..............so option A may make the system oscillate as "00" is the final input. In option D, after "00" flipflop output may oscillate but after "11", it will be stabilized.

Test: Synchronous & Asynchronous Circuits - Question 9

The below figure shows four D-type flip-flops connnected as a shift register using an XOR gate. The initial state and three subsequent states for three clock pulses are also given.



The state after the fourth clock pulse is

Detailed Solution: Question 9


Test: Synchronous & Asynchronous Circuits - Question 10

Consider the circuit given below with initial state . The state of the circuit is given by the value 

Which one of the following is correct state sequence of the circuit?

Detailed Solution: Question 10



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