Test: Static & Large Memories - Computer Science Engineering (CSE) MCQ
25 Questions MCQ Test - Test: Static & Large Memories
The duration between the read and the mfc signal is ______
The minimum time delay between two successive memory read operations is ______
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__________ is the bootleneck, when it comes computer performance.
The logical addresses generated by the cpu are mapped onto physical memory by ____
The cells in a row are connected to a common line called ______
A 16 X 8 organisation of memory cells, can store upto _____
A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organised into _____
Circuits that can hold their state as long as power is applied is _______
The number of external connections required in 16 X 8 memory organisation is _____
The advantage of CMOS SRAM over the transistor one’s is _________
In a 4M-bit chip organisation has a total of 19 external connections.then it has _______ address if 8 data lines are there.
The chip can be disabled or cut off from external connection using ______
To organise large memory chips we make use of ______
The less space consideration as lead to the development of ________ (for large memories).
The higher order bits of the address are used to _____
The address lines multiplexing is done using ______
The controller multiplexes the addresses after getting the _____ signal.
Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read opeartion. Then the refresh overhead of the chip is ______
When DRAM’s are used to build a complex large memory,then the controller only provides the refresh counter.
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