Test: Interrupt And Stack Of 8051 - Computer Science Engineering (CSE) MCQ

INT0(active low) and INT1(active low) are two external interrupt inputs provided by 8051.

The interrupts, INT0(active low) and INT1(active low) are processed internally by the flags IE0 and IE1.

If the interrupts are programmed as edge sensitive, the flags IE0 and IE1 are automatically cleared after the control is transferred to respective vector.

 If the interrupts are programmed as level sensitive, then the flags IE0 and IE1 are controlled by external interrupt sources themselves.

In counter mode, the pulses are counted at T0 or T1 pin.

As 8051 stack operations are 8-bit wide i.e. in an operation using PUSH or POP instruction, one byte of data is stored on a stack or retrieved from the stack. For implementing 16-bit operations, two 8-bit operations are cascaded.

The PUSH instruction follows two steps.
1. Increment stack by 1
2. Store 8-bit content of the 8-bit address specified in the instruction to the address pointed to by SP.

The POP instruction follows two steps.
1. Store the contents of top of stack pointed to by SP register to the 8-bit memory specified in the instruction.
2. Decrement stack by 1.

The 8051 stack is opposite to that in 8085 or 8086 i.e. in 8085 it is auto-decrement while in 8051 it is auto-increment during PUSH operations.

The stack pointer(SP) is an 8-bit register and is initialized to internal RAM address 07H after reset.