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Test: Power Control Register - Computer Science Engineering (CSE) MCQ


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10 Questions MCQ Test - Test: Power Control Register

Test: Power Control Register for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Test: Power Control Register questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Power Control Register MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Power Control Register below.
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Test: Power Control Register - Question 1

 The power control register is

Detailed Solution for Test: Power Control Register - Question 1

The power control register is used for power saving during idle state of the microcontroller and eventual power off to the microcontroller chip. It has SMOD bit which is used to double the baud rate.

Test: Power Control Register - Question 2

The state of signals in idle mode is

Detailed Solution for Test: Power Control Register - Question 2

ALE and PSEN(active low) remain high in Idle mode.

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Test: Power Control Register - Question 3

To come out of idle mode, the external interrupt that is enabled is

Detailed Solution for Test: Power Control Register - Question 3

To come out of idle mode, any external interrupt that is enabled like SI(Serial), INT0 and INT1.

Test: Power Control Register - Question 4

 The microcontroller enters into power down mode when

Detailed Solution for Test: Power Control Register - Question 4

If the PD bit of PCON register is set, it enters power down mode.

Test: Power Control Register - Question 5

The clock signal is disabled to all parts of 8051 in

Detailed Solution for Test: Power Control Register - Question 5

In power down mode, the clock signal to all parts of 8051 chip is disabled.

Test: Power Control Register - Question 6

 During power down to save battery, the supply voltage can be reduced to a value of

Detailed Solution for Test: Power Control Register - Question 6

The supply voltage can be reduced to a value of around 2 volts, during power down to save battery.

Test: Power Control Register - Question 7

The signal that only pulls the microcontroller(8051) out of the power down mode is

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Only Reset signal can pull 8051 out of the power down mode.

Test: Power Control Register - Question 8

The state of signals in power down mode is

Detailed Solution for Test: Power Control Register - Question 8

ALE and PSEN(active low) remain low in power down mode of 8051.

Test: Power Control Register - Question 9

 In power down mode,

Detailed Solution for Test: Power Control Register - Question 9

In power down mode, the clock signal is disabled and all the port pins and respective SFRs maintain their logic levels.

Test: Power Control Register - Question 10

The SMOD bit is used to

Detailed Solution for Test: Power Control Register - Question 10

The SMOD bit is used to double the baud rate.

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